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ORCA(R) ORT42G5 and ORT82G5
0.6 to 3.7 Gbps XAUI and FC FPSCs
July 2008 Data Sheet DS1027
Introduction
Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORT42G5 and ORT82G5 are made up of SERDES transceivers containing four and eight channels respectively. Each channel operates at up to 3.7 Gbps across 26 inches of FR-4 backplane, with a full-duplex synchronous interface with built-in Rx Clock and Data Recovery (CDR), and transmitter preemphasis, along with more than 400K usable FPGA system gates. The CDR circuitry available from Lattice's high-speed I/O portfolio (sysHSITM), has already been proven in numerous applications, to create interfaces for SONET/SDH, Fibre Channel, and Ethernet (GbE, 10 GbE) applications. Designers can also use these devices to drive high-speed data transfer across buses within any generic system. For example, designers can build a bridge for 10 G Ethernet: the high-speed SERDES interfaces can implement a XAUI interface with a configurable back-end interface such as XGMII. The ORT42G5 and ORT82G5 can also be used to provide a full 10 G backplane data connection and, in the case of the ORT82G5, provide both work and protection links between a line card and switch fabric. The ORT42G5 and ORT82G5 provide a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT42G5 and ORT82G5 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The device supports embedded 8b/10b encoding/decoding and link state machines for 10 G Ethernet, and Fibre Channel. The ORT82G5 is pinout compatible with a sister device, the ORSO82G5, which implements eight channels of SERDES with SONET scrambling and cell processing. The ORT42G5 is pin compatible with the ORSO42G5, which implements four channels of SERDES with SONET scrambling and cell processing. Table 1. ORCA ORT42G5 and ORT82G5 Family - Available FPGA Logic
Device ORT42G5 ORT82G5 PFU Rows 36 36 PFU Columns 36 36 Total PFUs 1296 1296 FPGA Max. User I/O 204 372 LUTs 10,368 10,368 EBR Blocks2 12 12 EBR Bits2 (K) 111 111 FPGA System Gates (K)1 333-643 333-643
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The system gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR usage and two PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and four PLLs. 2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
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DS1027_07.0
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Reference Clock Requirements .................... 37 Synthesized and Recovered Clocks ............. 37 Internal Clock Signals at the FPGA/Core Interface for the ORT42G5 ................................................. 38 Transmit and Receive Clock Rates............... 39 Transmit Clock Source Selection .................. 39 Recommended Transmit Clock Distribution for the ORT42G5 .................................... 39 Multi-Channel Alignment Clocking Strategies for the ORT42G5 ................... 41 Internal Clock Signals at the FPGA/Core Interface for the ORT82G5 ................................................. 43 Transmit and Receive Clock Rates............... 44 Transmit Clock Source Selection .................. 44 Recommended Transmit Clock Distribution for the ORT82G5 .................................... 45 Multi-Channel Alignment Clocking Strategies for the ORT82G5 ................... 47 Reset Operation ......................................................... 49 Start Up Sequence for the ORT42G5 ........... 50 Start Up Sequence for the ORT82G5 ........... 51 Test Modes ................................................................ 52 Loopback Testing.......................................... 52 High-Speed Serial Loopback at the CML Buffer Interface ....................................... 53 Parallel Loopback at the SERDES Boundary ................................................ 54 Parallel Loopback at MUX/DEMUX Boundary, Excluding SERDES ............... 55 SERDES Characterization Test Mode (ORT82G5 Only)..................................... 55 Embedded Core Block RAM ...................................... 56 Memory Maps ............................................................ 59 Definition of Register Types .......................... 59 ORT42G5 Memory Map................................ 59 ORT82G5 Memory Map................................ 67 Recommended Board-level Clocking for the ORT42G5 and ORT82G5 ................. 73 Absolute Maximum Ratings ....................................... 75 Recommended Operating Conditions ........................ 75 SERDES Electrical and Timing Characteristics ......... 75 High Speed Data Transmitter........................ 76 High Speed Data Receiver............................ 77 External Reference Clock ............................. 79 Embedded Core Timing Characteristics ....... 79 Pin Descriptions ......................................................... 80 Power Supplies for ORT42G5 AND ORT82G5.......... 85 Power Supply Descriptions ........................... 85 Recommended Power Supply Connections............................................ 85 Recommended Power Supply Filtering Scheme................................................... 85 Package Information .................................................. 87 Package Pinouts ........................................... 87 2
Table of Contents
Introduction .................................................................. 1 Table of Contents......................................................... 2 Embedded Function Features...................................... 4 Programmable Features .............................................. 5 Programmable Logic System Features........................ 6 Description ................................................................... 7 What is an FPSC?........................................... 7 FPSC Overview............................................... 7 FPSC Gate Counting ...................................... 7 FPGA/Embedded Core Interface .................... 7 FPSC Design Kit ............................................. 7 FPGA Logic Overview..................................... 8 PLC Logic........................................................ 8 Programmable I/O........................................... 8 Routing............................................................ 9 System-Level Features ................................................ 9 Microprocessor Interface................................. 9 System Bus ................................................... 10 Phase-Locked Loops .................................... 10 Embedded Block RAM .................................. 10 Configuration................................................. 10 Additional Information ................................... 11 ORT42G5/ORT82G5 Overview ................................. 11 Embedded Core Overview ............................ 11 Serializer and Deserializer (SERDES) .......... 11 MUX/DEMUX Block ...................................... 12 Multi-channel Alignment FIFOs..................... 12 XAUI and Fibre Channel Link State Machines....................................................... 12 FPGA/Embedded Core Interface .................. 12 Dual Port RAMs ............................................ 13 FPSC Configuration ...................................... 13 Backplane Transceiver Core Detailed Description .... 13 8b/10b Encoding and Decoding .................... 14 Transmit Path (FPGA to Backplane) Logic ... 16 8b/10b Encoder and 1:10 Multiplexer ........... 18 CML Output Buffer ........................................ 18 Receive Path (Backplane to FPGA) Logic .... 19 Link State Machines...................................... 24 XAUI Link Synchronization Function............. 25 Multi-channel Alignment............................................. 27 ORT42G5 Multi-channel Alignment .............. 27 ORT82G5 Multi-channel Alignment .............. 28 XAUI Lane Alignment Function (Lane Deskew) ....................................... 29 Mixing Half-rate, Full-rate Modes .................. 30 Multi-channel Alignment Configuration ...................... 30 ORT42G5 Configuration ............................... 30 ORT82G5 Configuration ............................... 31 ORT42G5 Alignment Sequence.................... 32 ORT82G5 Alignment Sequence.................... 33 Reference Clocks and Internal Clock Distribution...... 37
Lattice Semiconductor
Package Thermal Characteristics Summary .............................................. 114 JA .............................................................. 114 JC .............................................................. 114 JC .............................................................. 115 JB .............................................................. 115 FPSC Maximum Junction Temperature ...... 115 Package Thermal Characteristics ............... 115 Heat Sink Vendors for BGA Packages........ 115 Package Parasitics...................................... 116 Package Outline Drawings.......................... 116 Ordering Information ................................................ 117
ORCA ORT42G5 and ORT82G5 Data Sheet
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Embedded Function Features
* High-speed SERDES with programmable serial data rates over the range 0.6 to 3.7 Gbps. Operation has been demonstrated on design tolerance devices at 3.7 Gbps across 26 in. of FR-4 backplane and at 3.125 Gbps across 40 in. of FR-4 backplane across temperature and voltage specifications. * Asynchronous operation per receive channel with the receiver frequency tolerance based on one reference clock per block channels (separate PLL per channel). * Ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control registers. * Programmable one-half amplitude transmit mode for reduced power in chip-to-chip application. * Transmit preemphasis (programmable) for improved receive data eye opening. * 32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in FPGA logic. * Provides a 10 Gbps backplane interface to switch fabric. Also supports multiple port cards at 2.5 Gbps. * 3.125 Gbps SERDES compliant with XAUI serial data specification for 10 G Ethernet applications with protection. * IEEE 802.3ae compliant XAUI transceiver. Includes embedded IEEE 802.3ae-based XAUI link state machine. * Compliant to FC-0 specification for 1 Gbps, 2Gbps, 10 Gbps (FC-XAUI) modes. Includes Fibre Channel link state machine. * High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks. * SERDES has low-power CML buffers. Support for 1.5V/1.8V I/Os. Allows use with optical transceiver, coaxial copper media, shielded twisted pair wiring or high-speed backplanes such as FR-4. * Power down option of SERDES HSI receiver or transmitter on a per-channel basis. * Automatic lock to reference clock in the absence of valid receive data. * High-speed and low-speed loopback test modes. * Requires no external component for clock recovery and frequency synthesis. * SERDES characterization pins available to control/monitor the internal interface to one SERDES block (ORT82G5 only). * SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state. * Built-in boundary scan (IEEE (R) 1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES interface. * FIFOs can align incoming data either across all eight channels (ORT82G5 only), across one or two groups of four channels, or across two or four groups of two channels. Alignment is done either using comma characters or by using the /A/ character in XAUI mode. Optionally, the alignment FIFOs can be bypassed for asynchronous operation between channels. (Each channel includes its own clock and frame pulse or comma detect.) * Addition of two 4K x 36 dual-port RAMs with access to the programmable logic. * The ORT82G5 is pinout compatible to the ORCA ORSO82G5 SONET backplane driver FPSC. The ORT42G5 is pin compatible to the ORSO42G5.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Programmable Features
* High-performance programmable logic: - 0.16 m 7-level metal technology. - Internal performance of >250 MHz. - Over 400K usable system gates. - Meets multiple I/O interface standards. - 1.5V operation (30% less power than 1.8V operation) translates to greater performance. * Traditional I/O selections: - LVTTL (3.3V) and LVCMOS (2.5V and 1.8V) I/Os. - Per pin-selectable I/O clamping diodes provide 3.3V PCI compliance. - Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. - Two slew rates supported (fast and slew-limited). - Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time. - Fast open-drain drive capability. - Capability to register 3-state enable signal. - Off-chip clock drive capability. - Two-input function generator in output path. * New programmable high-speed I/O: - Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR. - Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable (on/off) internal parallel termination (100 ) is also supported for these I/Os. * New capability to (de)multiplex I/O signals: - New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate). - New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). * Enhanced twin-block Programmable Function Unit (PFU): - Eight 16-bit Look-Up Tables (LUTs) per PFU. - Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. - New register control in each PFU has two independent programmable clocks, clock enables, local SET/RESET, and data selects. - New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 1 MUX, new 8 1 MUX, and ripple mode arithmetic functions in the same PFU. - 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers. - Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed. - Flexible fast access to PFU inputs from routing. - Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. * Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. * Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. * SLIC provides eight 3-statable buffers, up to a 10-bit decoder, and PAL(R)-like AND-OR-Invert (AOI) in each programmable logic cell. * New 200 MHz embedded block-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be configured as:
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Lattice Semiconductor
- - - - - - - - - -
ORCA ORT42G5 and ORT82G5 Data Sheet
1--512 x 18 (block-port, two read/two write) with optional built in arbitration. 1--256 x 36 (dual-port, one read/one write). 1--1K x 9 (dual-port, one read/one write). 2--512 x 9 (dual-port, one read/one write for each). 2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). Supports joining of RAM blocks. Two 16 x 8-bit content addressable memory (CAM) support. FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9. Constant multiply (8 x 16 or 16 x 8). Dual variable multiply (8 x 8).
* Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are builtin system registers that act as the control and status center for the device. * Built-in testability: - Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG). - Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. - TS_ALL testability function to 3-state all I/O pins. - New temperature-sensing diode. * Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to 420 MHz. Multiplication of the input frequency up to 64x and division of the input frequency down to 1/64x possible. * New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers. * Per channel Pseudo-Random Bit Sequence (PRBS) generator and checker in FPGA logic.
Programmable Logic System Features
* PCI local bus compliant for FPGA I/Os. * Improved PowerPC (R) 860 and PowerPC II high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space provided. * New embedded system bus facilitates communication among the microprocessor interface, configuration logic, Embedded Block RAM, FPGA logic, and embedded standard cell blocks. * Variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. * Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. * New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for OR4E04). * New local clock routing structures allow creation of localized clock trees. * Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved setup/hold and clock to out performance. * New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest highspeed memory interfaces. * New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal logic.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Description
What is an FPSC?
FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the design effort savings of using soft Intellectual Property (IP) cores, and the speed, design density, and economy of ASICs.
FPSC Overview
Lattice's Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of Programmable Logic Cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the FPGA functionality is changed--all of the Series 4 FPGA capability is retained including: the Embedded Block RAMs, MicroProcessor Interface (MPI), boundary scan, etc. The columns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins retain their FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates. Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more siliconarea efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater number of interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and accounted for in the Lattice ispLEVERTM System software. Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-master 32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic functions including the Embedded Block RAMs and the microprocessor interface. Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the FPGA as a system. For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER System software and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC configuration manager, complied Verilog simulation models, HSPICE and/or IBIS models for I/O buffers, and complete online documentation. The kit's software coupled with the design environment, provides a seamless FPSC design environment. More information can be obtained by visiting the Lattice web site at www.latticesemi.com or contacting a local sales office.
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Lattice Semiconductor FPGA Logic Overview
ORCA ORT42G5 and ORT82G5 Data Sheet
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades. The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge of FPGA and ASIC designs. Modular hardware and software technologies enable System-on-Chip integration with true plug-and-play design implementation. The architecture consists of four basic elements: Programmable Logic Cells (PLCs), Programmable I/O cells (PIOs), Embedded Block RAMs (EBRs), plus supporting system-level features. These elements are interconnected with a rich routing fabric of both global and local wires. An array of PLCs is surrounded by common interface blocks which provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. Each PLC contains a PFU, SLIC, local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. Large blocks of 512 x 18 block-port RAM complement the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the MPI, PLLs, and the Embedded System Bus (ESB).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional Flip-Flop that may be used independently or with arithmetic functions. The PFU is organized in a twin-block fashion; two sets of four LUTs and FFs that can be controlled independently. Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidirectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for realworld system performance.
Programmable I/O
The Series 4 PIO addresses the demand for the flexibility to select I/Os that meet system interface requirements. I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features which allow the user the flexibility to select new I/O types that support High-Speed Interfaces. Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset, and global set/reset. On the input side, each PIO contains a programmable latch/Flip-Flop which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer with a PFU. On the output side of each PIO, an output from the PLC array can be routed to each output Flip-Flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3state signal can be registered or nonregistered. The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and out of the I/O buffers on both edges of the clock. The new programmable I/O cell allows designers to select I/Os which meet many new communication standards permitting the device to hook up directly without any external interface translation. They support traditional FPGA standards as well as high-speed, single-ended, and differential-pair signaling. Based on a programmable, bank-oriented I/O ring architecture, designs can be implemented using 3.3V, 2.5V, 1.8V, and 1.5V referenced output levels.
Routing
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can be sourced from any I/O pin, PLLs, or the PLC logic. The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins.
System-Level Features
The Series 4 also provides system-level functionality by means of its microprocessor interface, Embedded System Bus, block-port Embedded Block RAMs, universal programmable Phase-Locked Loops, and the addition of highly tuned networking specific Phase-locked Loops. These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed networking systems.
Microprocessor Interface
The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-, 16, and 32-bit interfaces with optional parity to the Motorola(R) PowerPC 860 bus, it can be used for configuration and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4 Embedded System Bus at 66 MHz performance. A system-level microprocessor interface to the FPGA user-defined logic following configuration, through the system bus, including access to the Embedded Block RAM and general user-logic, is provided by the MPI. The MPI supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes).
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Lattice Semiconductor System Bus
ORCA ORT42G5 and ORT82G5 Data Sheet
An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, configuration logic, FPGA control, status registers, Embedded Block RAMs, as well as user logic. Utilizing the AMBA specification Rev 2.0 AHB protocol, the Embedded System Bus offers arbiter, decoder, master, and slave elements. Master and slave elements are also available for the user-logic and a slave interface is used for control and status of the embedded backplane transceiver portion of the device. The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset functions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the microprocessor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from routing, or from the port clock (for JTAG configuration modes).
Phase-Locked Loops
Up to eight PLLs are provided on each Series 4 device, with four user PLLs generally provided for FPSCs. Programmable PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Each PPLL is capable of manipulating and conditioning clocks from 20 MHz to 200 MHz. Frequencies can be adjusted from 1/8x to 8x, the input clock frequency. Each programmable PLL provides two outputs that have different multiplication factors but can have the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic input buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences.
Embedded Block RAM
New 512 x 18 block-port RAM blocks are embedded in the FPGA core to significantly increase the amount of memory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. Additional logic has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable multiply functions. The user can configure FIFO blocks with flexible depths of 512K, 256K, and 1K including asynchronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiple of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiple of two 8-bit numbers (16bit output). On-the-fly coefficient modifications are available through the second read/write port. Two 16 x 8-bit CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can also be preloaded at device configuration time.
Configuration
The FPGAs functionality is determined by internal configuration RAM. The FPGAs internal initialization/configuration circuitry loads the configuration data at power up or under system control. The configuration data can reside externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for configuring FPGAs. The RAM is loaded by using one of several configuration modes. Supporting the traditional master/slave serial, master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its microprocessor interface and Embedded System Bus to perform both programming and readback. Daisy chaining of multiple devices and partial reconfiguration are also permitted. Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory as well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE 1149.2) port is also available meeting In-System Programming (ISPTM) standards (IEEE 1532 Draft).
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Lattice Semiconductor Additional Information
ORCA ORT42G5 and ORT82G5 Data Sheet
Contact your local Lattice representative for additional information regarding the ORCA Series 4 FPGA devices, or visit the Lattice web site at www.latticesemi.com.
ORT42G5/ORT82G5 Overview
The ORT42G5 and ORT82G5 FPSCs provide high-speed backplane transceivers combined with FPGA logic. They are based on the 1.5V OR4E04 ORCA FPGA and have 36 x 36 arrays of Programmable Logic Cells (PLCs). The embedded core, which contains the backplane transceivers is attached to the right side of the device and is integrated directly into the FPGA array. A top level diagram of the basic chip configuration is shown in Figure 1.
Embedded Core Overview
The embedded core portions of the ORT42G5 and ORT82G5 contain respectively four or eight Clock and Data Recovery (CDR) macrocells and Serialize/Deserialize (SERDES) blocks and support 8b/10b (IEEE 802.3.2002) encoded serial links. It is intended for high-speed serial backplane data transmission. Figure 1 shows the ORT42G5 and ORT82G5 top level block diagram and the basic data flow. Boundary scan for the ORT42G5/ORT82G5 only includes programmable I/Os and does not include any of the embedded block I/Os. Figure 1. ORT42G5/ORT82G5 Top Level Block Diagram
0.6 Gbps TO 3.7 Gbps DATA STANDARD
FPGA I/Os
ORCA SERIES 4 FPGA LOGIC
8b/10b BYTEDECODER/ENCODER WIDE 4:1 MUX/1:4 DEMUX AND MULTI-CHANNEL DATA ALIGNMENT FIFOs
SERDES w/ CLOCK/DATA RECOVERY
CML I/Os
4 or 8 FULLDUPLEX SERIAL CHANNELS
0.6 Gbps TO 3.7 Gbps DATA
The serial channels can each operate at up to 3.7 Gbps (2.96 Gbps data rate) with a full-duplex synchronous interface with built-in clock recovery (CDR). The 8b/10b encoding provides guaranteed ones density for the CDR, byte alignment, and error detection. The core is also capable of frame synchronization and physical link monitoring and contains independent 4k x 36 RAM blocks. Overviews of the various blocks in the embedded core are presented in the following paragraphs.
Serializer and Deserializer (SERDES)
The SERDES portion of the core contains two transceiver blocks for serial data transmission at a selectable data rate of 0.6 to 3.7 Gbps. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core blocks and high-speed CML interfaces to the serial links. The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts highspeed (up to 3.7 Gbps) serial data. Based on data transitions, the receiver locks an analog receive PLL for each channel to retime the data, then demultiplexes the data down to parallel bytes and an accompanying clock. The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.7 Gbps serial data for offchip communication. The transmitter generates the necessary 3.7 GHz clocks for operation from a lower speed reference clock.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
The transceivers are controlled and configured through the system bus in the FPGA logic and through the external 8-bit microprocessor interface of the FPGA. Each channel has associated dedicated registers that are readable and writable. There are also global registers for control of common circuitry and functions. The SERDES performs 8b/10b encoding and decoding for each channel. The 8b/10b transmission code can support either Ethernet or Fibre Channel specifications for serial encoding/decoding, special characters, and error detection. The user can disable the 8b/10b decoder to receive raw 10-bit words which will be rate reduced by the SERDES. If this mode is chosen, the user must bypass the multi-channel alignment FIFOs. The SERDES block contains its own dedicated PLLs for both transmit and receive clock generation. The user provides a reference clock of the appropriate frequency. The receiver PLLs extract the clock from the serial input data and retime the data with the recovered clock.
MUX/DEMUX Block
The MUX/DEMUX block converts the data format for the high speed serial links to a wide, low-speed format for crossing the CORE/FPGA interface. The intermediate interface to the SERDES macrocell runs at 1/10th the bit rate of the data lane. The MUX/DEMUX converts the data rate and bus width so the interface to the FPGA core can run at 1/4th this intermediate frequency, giving a range of 25.0-92.5 MHz for the data rates into and out of the FPGA logic.
Multi-channel Alignment FIFOs
In the ORT82G5, the eight incoming data channels (four per SERDES block) can be independent of each other or can be synchronized in several ways. Two channels within a SERDES block can be aligned together; channels A and B and/or channels C and D. Alternatively, four channels in a SERDES block can be aligned together to form a communication channel with a bandwidth of 10 Gbps. Finally, the alignment can be extended across both SERDES blocks to align all eight channels. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. In the ORT42G5, the four incoming data channels (two per SERDES block) can be independent of each other or can be synchronized in two ways. Two channels, channels C and D, within either SERDES block can be aligned together. Alternatively, all four channels can be aligned together to form a communication channel with a bandwidth of 10 Gbps. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels.
XAUI and Fibre Channel Link State Machines
Two separate link state machines are included in the architecture. A XAUI link state machine is included in the embedded core modeled after the IEEE 802.3ae standard. A separate state machine for Fibre Channel is also implemented.
FPGA/Embedded Core Interface
In 8b/10b mode, the FPGA logic will receive/transmit 32-bits of data (up to 92.5 MHz) and 4 K_CTRL bits from/to the embedded core. There are 8 data streams in each direction plus additional timing, status and control signals. Data sent to the FPGA can be aligned using comma (/K/) characters or /A/ character as specified either by Fibre Channel or by IEEE 802.3ae for XAUI based interfaces. The alignment character is made available to the FPGA along with the data. The special characters K28.1, K28.5 and K28.7 are treated as valid comma characters by the SERDES. If the receive channel alignment FIFOs are bypassed, then each channel will provide its own receive clock in addition to data and comma character detect signals. If the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in 8b/10b bypass mode.
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Lattice Semiconductor Dual Port RAMs
ORCA ORT42G5 and ORT82G5 Data Sheet
In addition to the backplane interface blocks, there are two independent memory blocks in the ASB. Each memory block has a capacity of 4k words by 36 bits. It has one read port, one write port, and four byte-write-enable (activelow) signals. The read data from the memory block is registered so that it works as a pipelined synchronous memory block.
FPSC Configuration
Configuration of the ORT42G5 and ORT82G5 occurs in two stages: FPGA bitstream configuration and embedded core setup. Prior to becoming operational, the FPGA goes through a sequence of states, including power up, initialization, configuration, start-up, and operation. The FPGA logic is configured by standard FPGA bit stream configuration means as discussed in the Series 4 FPGA data sheet. After the FPGA configuration is complete, the options for the embedded core are set based on the contents of registers that are accessed through the FPGA system bus. The system bus itself can be driven by an external PowerPC compliant microprocessor via the MPI block or via a user master interface in FPGA logic. A simple IP block that drives the system by using the user register interface and very little FPGA logic is available in the MPI/System Bus Technical Note. This IP block sets up the embedded core via a state machine and allows the ORT42G5 and ORT82G5 to work in an independent system without an external microprocessor interface.
Backplane Transceiver Core Detailed Description
The following sections describe the various logic blocks in the Embedded Core portion of the FPSC. The FPGA section of the FPSC is identical to an ORCA OR4E04 FPGA except that the pads on one edge of the FPGA chip are replaced by the Embedded Core. For a detailed description of the programmable logic functions, please see the ORCA Series 4 FPGA Data Sheet and related application and technical notes. The major functional blocks in the Embedded Core include: * Two SERializer-DESerializer (SERDES) blocks and Clock and Data Recovery (CDR) circuitry * 8b/10b encoder/decoders * Transmit pre-emphasis circuitry * 4-to-1 multiplexers (MUX) and 1-to-4 demultiplexers (DEMUX) * Fibre channel synchronization state machine * XAUI link alignment state machine * Alignment FIFOs * Embedded 4K x 36 RAM blocks (independent from transceiver logic). A top level block diagram of the Embedded Core Logic is shown in Figure 2. The Embedded RAM blocks are not shown. The external pins for the Embedded Core are listed later in this data sheet in Table 41 and the signals at the Transceiver Embedded Core/FPGA interface for the ORT42G5 are listed in Table 8, Table 9 and Table 11; and for the ORT82G5, in Table 8, Table 10 and Table 12.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 2. Top Level Block Diagram, Embedded Core Logic (Channel AC)
RCK78A TCK78A RSYS_CLK_A2 MRWDAC[39:0] CV_SELAC RWCKAC Multi Channel Alignment Block Receive Channel AC Link State Machine DEMUX Block RX SERDES Block HDIN[P:N]_AC
2
REFCLK[P:N]_A Common Logic, Block A
2
2:1 MUX (x40)
TSYS_CLK_AC TWDAC[31:0] TCOMMAC[3:0] Interface and MUX Block Transmit Channel AC HDOUT[P:N]_AC TX SERDES 2 Block
Backplane Serial Links
FPGA Logic
. . .
Next Channel
. . .
Last Channel (BD)
The Embedded Core provides transceiver functionality for four or eight serial data channels and is organized into two blocks, each supporting two or four channels. Each channel is identified by both a block identifier [A:B] and a channel identifier [A:D]. In the ORT42G5 only the channel identifiers C and D are used. (This naming convention follows that of the ORT82G5). The data channels can operate independently or they can be combined together (aligned) to achieve higher bit rates. The mode operation of the core is defined by a set of control registers, which can be written through the system bus interface. Also, the status of the core is stored in a set of status registers, which can be read through the system bus interface. The transmitter section for each channel accepts 40 bits of data or 32 bits of data and eight control/status bits from the FPGA logic and optionally encodes the data using 8b/10b encoding. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to synthesize the internal high-speed serial bit clock. The data is then serialized and the serialized data are available at the differential CML output terminated in 86 to drive either an optical transmitter or coaxial media or circuit board/backplane. The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the clock recovery section which generates a recovered clock and retimes the data. The retimed data are also deserialized and optionally 8b/10b decoded. The receiver also optionally recognizes the comma characters or code violations and aligns the bit stream to the proper word boundary. The resulting parallel data is optionally passed to the multi-channel alignment block before it is presented to the FPGA logic.
8b/10b Encoding and Decoding
In 8b/10b mode, the FPGA logic will receive/transmit 32 bits of data and 4 K_CTRL bits from/to the embedded core. In the transmit direction, four additional input bits force a negative disparity present state. The embedded core logic will encode the data to or decode the data from a 10-bit format according to the FC-PH ANSI X3.230:1994 standard (which is also the encoding used by the IEEE 802.3ae Ethernet standard). This encoding/decoding scheme also allows for the transmission of special characters and supports error detection.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Following the definitions and conventions used in defining the 8b/10b coding rules, each valid coded character has a name corresponding to its 8-bit binary value: * Dxx.y for data characters * Kxx.y for special characters * xx = the 5-bit input value, base 10, for bits ABCDE * y = the 3-bit input value, base 10, for bits FGH An 8b/10b encoder is designed to maintain a neutral average disparity. Disparity is the difference between the number of 1s and 0s in the encoded word. Neutral disparity indicates the number of 1s and 0s are equal. Positive disparity indicates more 1s than 0s. Negative disparity indicates more 0s than 1s. The average disparity determines the DC component of the signals on the serial line. Running disparity is a record of the cumulative disparity of every encoded word, and is tracked by the encoder. In order to maintain neutral disparity, two different codings are defined for each data value. The 8b/10b encoder in the transmit path selects between (+) and (-) encoded word based on calculated disparity of the present data to maintain neutral disparity In the receive path, the clock and data recovery blocks retime the incoming data and 8b/10b decoders generate 8bit data based on the received 10-bit data. A sequence of valid 8b/10b coded characters has a maximum run length of 5 bits (i.e., 5 consecutive ones or 5 consecutive zeros before a mandatory bit transition). This assures adequate transitions for robust clock recovery. The recovered data is aligned on a 10-bit boundaries by detecting and aligning to special characters in the incoming data stream. Data is word aligned using the comma (/K/) character. A comma character is a special character that contains a unique pattern (0011111 or its complement 1100000) in the 10-bit space that makes it useful for delimiting word boundaries. The special characters K28.1, K28.5 and K28.7 contain this comma sequence and are treated as valid comma characters by the SERDES. The following table shows all of the valid special characters. All of the special characters are made available to the FPGA logic; however only the comma characters are used by the SERDES logic. The different codings that are possible for each data value are shown as encoded word (+) and encoded word (-). The table also illustrates the 8b/10b bit labeling convention. The bit positions of the 8-bit characters are labeled as H,G,F,E,D,C,B and A and the bit positions of the 10-bit encoded characters are labeled as a, b, c, d, e, i, f, g, h, and j. The encoded words are transmitted serially with bit `a' transmitted first and bit `j' transmitted last. Table 2. Valid Special Characters
K Character K28.0 K28.1 /comma/ K28.2 K28.3 /A/ K28.4 K28.5 /comma/ K28.6 K28.7 /comma/ K23.7 K27.7 K29.7 K30.7 HGF EDCBA 765 43210 000 11100 001 11100 010 11100 011 11100 100 11100 101 11100 110 11100 111 11100 111 10111 111 11011 111 11101 111 11110 Encoded Word (-) K Control 1 1 1 1 1 1 1 1 1 1 1 1 abcdei fghj 001111 0100 001111 1001 001111 0101 001111 0011 001111 0010 001111 1010 001111 0110 001111 1000 111010 1000 110110 1000 101110 1000 011110 1000 Encoded Word (+) abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 1001 110000 0111 000101 0111 001001 0111 010001 0111 100001 0111
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Lattice Semiconductor Transmit Path (FPGA to Backplane) Logic
ORCA ORT42G5 and ORT82G5 Data Sheet
The transmitter section accepts four groups of either 8-bit unencoded data or 10-bit encoded data at the parallel interface to the FPGA logic. It also uses the reference clock, REFCLK[P:N]_[A:B] to synthesize an internal highspeed serial bit clock. The serialized transmitted data are available at the differential CML output pins to drive either an optical transmitters, coaxial media or a circuit board backplane. As shown in Figure 3, the basic blocks in the transmit path include: Embedded Core/FPGA interface and 4:1 multiplexer * Low speed parallel core/FPGA interface * 4:1 multiplexer Transmit SERDES * 8b/10b Encoder * 10:1 Multiplexer * CML Output Buffer Detailed descriptions of the logic blocks are given in following sections. Detailed descriptions of transmit clock distribution, including the transmit PLL are given in later sections of this data sheet. Figure 3. Basic Logic Blocks, Transmit Path, Single Channel (Typical Reference Clock Frequency) FPGA Logic
TWDxx[31:0] TCOMMAxx[3:0] TBIT9xx[3:0] TSYS_CLK_xx
32 4 4
For ORT42G5: xx = [AC, AD, BC or BD] For ORT82G5: xx = [AA, AB, ... BD]
Backplane Serial Link TX SERDES Block
Interface and MUX Block
STBD_xx[7:0] 8 8-bit data STBD_xx[8]
FIFO
4:1 MUX (x9)
K-control
8B/10B Encoder (with bypass)
HDOUTP_xx
10:1 MUX
STBD_xx[9]
Force-ve disparity
CML Buffer with Preemphasis
HDOUTN_xx
/4
STBC311_xx
312.5 MHz
PLL
Logic Common to Block
MUX
REFCLKP_[A:B]
78.125 MHz
TCKSEL[0:1][A:B]
{
TCK78[A:B]
From other channel or channels From Control Register
To other channel or channels
{
CML Buffer
REFCLKN_[A:B]
156.25 MHz
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Embedded Core/FPGA Logic Interface and 4:1 Multiplexer These blocks provide the data formatting and transmit data and clock signal transfers between the Embedded Core and the FPGA Logic. Control and status registers in the FPGA portion of the chip contain to control the transmit logic and record status. These bits are passed to the core using the FPGA System Bus and are described in later sections of this data sheet. The low-speed transmit interface consists of a clock and 4 data bytes, each with an accompanying control bit. The data bytes are conveyed to the MUX via the TWDxx[31:0] ports (where xx represents the channel label [AA,...,BD] or [AC, AD, BC, BD]). The control bits are TCOMMAx[3:0] which define whether the input byte is to be interpreted as data or as a special character and TBIT9xx[3:0] which are used to force a negative disparity present state. The data and control signals are synchronized to the transmit clock, TSYS_CLK_xx. Both the data and control are strobed into the core on the rising edge of TSYS_CLK_xx. Note that each TBIT9xx[3:0] controls the disparity of the encoded version of its corresponding data byte. Setting bit TBIT9AC[3] to 1, for instance, will force the 8b/10b encoder to assess a current negative running disparity state. This will cause it to encode TWDAC[31:24] positively (more 1's than 0's). Setting TBIT9xx to 0 will leave the encoder free to alternate between positive and negative encoding to maintain a zero running disparity. The MUX is responsible for taking 40 bits of data/control at the low-speed transmit interface and up-converting it to 10 bits of data/control at the SERDES transmit interface. The MUX has 2 clock domains - one based on the clock received from the SERDES block and a second that comes from the FPGA at 1/4 the frequency of the SERDES clock. The time sequence of interleaving data/control values is shown in Figure 4. Figure 4. Transmit MUX Block Timing - Single Channel
TWDxx[31:24], TCOMMAxx[3] TBIT9xx[3] TWDxx[23:16], TCOMMAxx[2] TBIT9xx[2] TWDxx[15:8], TCOMMAxx[1] TBIT9xx[1] TWDxx[7:0], TCOMMAxx[0] TBIT9xx[0] p p 7-0, 8 p 9 t t 7-0, 8 t 9
q qq 7-0, 8 9
x x 7-0, 8
x 9
r
r 7-0, 8
r
9
y y 7-0, 8
y 9
s ss 7-0, 8 9
zz z 7-0, 8 9
LATENCY = 4 TSYS_CLK_xx CLOCKS
10-bit wide data p q r s t x y z
STBDxx[9:0]
TSYS_CLK_xx
SERDES Block The SERDES block accepts either 8-bit data to be encoded or 10-bit unencoded data at the parallel input port from the MUX/DEMUX block. It also accepts the reference clock at the REFCLK_[A:B] input and uses this clock to synthesize the internal high-speed serial bit clock. The internal STBC311xx clock is derived from the reference clock. The frequency of this clock depends on the setting of the half-rate/full-rate control bit setting the mode of the SERDES and the frequency of the REFCLK_[A:B] and/or that of the high-speed serial data. A falling edge on the STBC311xx clock port will cause a new data character to be transferred into the SERDES block. The latency from the SERDES block input to the high-speed serial output is 5 STBC311xx clock cycles, as shown in Figure 5.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 5. Transmit Path Timing - Single SERDES Channel
STBDxx[9:0] p q r s t x y z
..... .....
STBC311xx
LATENCY = 5 STBC311x CLOCKS HDOUT_xx
.....
pppp pppppp 0123 456789
Each block also sends a clock to the FPGA logic. This clock, TCK78[A,B], is sourced from one of the four MUX blocks and has the same frequency as TSYS_CLK_xx, but arbitrary phase. Within each MUX block, the low frequency clock output is obtained by dividing by 4 the SERDES STBC311x clock which is used internally to synchronize the transmit data words. TCKSEL control bits select the channel to source TCK78[A:B]. The internal signals STBDxx[9:0] (where xx is represents AA...BD or AC, AD, BC, BD) from the MUX block carry unencoded character data and control bits. The 10th bit (STBDxx[9]) of each data lane into the SERDES is used to force a negative disparity present state.
8b/10b Encoder and 1:10 Multiplexer
The 8b/10b encoder encodes the incoming 8-bit data into a 10-bit format as described previously. The input signals to the block, STBDxx[7:0] are used for the 8-bit unencoded data. STBDxx[8] is used as the K_control input to indicate whether the 8 data bits need to be encoded as special characters (K_control = 1) or as data characters (K_control = 0). When STBDxx[9:0] = 1, a negative disparity present state is forced. When the encoder is bypassed STBDxx[9:0] serve as the data bits for the 10-bit unencoded data. Within the definition of the 8b/10b transmission code, the bit positions of the 10-bit encoded transmission characters are labeled as a, b, c, d, e, i, f, g, h, and j in that order. Bit a corresponds to STBDxx[0], bit b to STBDxx[1], bit c to STBDxx[2], bit d to STBDxx[3], bit e to STBDxx[4], bit i to STBDxx[5], bit f to STBDxx[6], bit g to STBDxx[7], bit h to STBDxx[8], and bit j to STBDxx[9]. The 10-bit wide parallel data is converted to serial data by the 10:1 Multiplexer. The serial data are then sent to the CML output buffer and are transmitted serially with STBDxx[0] transmitted first and STBDxx[9] transmitted last.
CML Output Buffer
The transmitter's CML output buffer is terminated on-chip in 86 ohms to optimize the data eye as well as to reduce the number of discrete components required. The differential output swing reaches a maximum of 1.2 VPP in the normal amplitude mode. A half amplitude mode can be selected via configuration register bit HAMP_xx. Half amplitude mode can be used to reduce power dissipation when the transmission medium has minimal attenuation or for testing of the integrity (loss) of the physical medium. A programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maximize the data eye opening at the far-end receiver. Preemphasis is particularly useful when the data are transmitted over backplanes or low-quality coax cables which have a frequency-dependent amplitude loss. For example, for FR4 material at 2.5 GHz, the attenuation compared to the 1.0 GHz value is about 3 dB. The attenuation is a result of skin effect loss of the PCB conductor and the dielectric loss of the PCB substrate. This attenuation causes intersymbol interface which results in the closing of the data eye opening at the receiver.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Since this effect is predictable for a given type of PCB material, it is possible to compensate for this effect in two ways - transmitter preemphasis and receiver equalization. Each of these techniques boosts the high frequency components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better power utilization. It also gives a better signal-to-noise ratio because receiver equalization amplifies both the signal and the noise at the receiver Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also degrade the data eye opening at the receiver. In the ORT42G5 and ORT82G5 the degree of transmit preemphasis can be programmed with a two-bit control from the microprocessor interface as shown in Table 3. The high-pass transfer function of the preemphasis circuit is given by the following equation, where the value of a is shown in Table 3. H(z) = (1 - az -1) Table 3. Preemphasis Settings
PE1 0 0 1 1 PE0 0 1 0 1 Amount of Preemphasis (a) 0% (No Preemphasis) 12.5% 12.5% 25%
(1)
Receive Path (Backplane to FPGA) Logic
The receiver section receives high-speed serial data at the external differential CML input pins. These data are fed to the clock recovery section which generates a recovered clock and retimes the data. Therefore the receive clocks are asynchronous between channels. The retimed data are deserialized and presented as an 8-bit decoded or a 10-bit unencoded parallel data on the output port. The receiver also optionally recognizes comma characters, detects code violations and aligns the bit stream to the proper word boundary. As shown in Figure 6, the basic blocks in the receive path include: Receive SERDES Block * CML input buffer * Receive PLL * 1:10 demultiplexer (DEMUX) * Clock and Data Recovery (CDR) section * 10b/8b decoder * 1:4 demultiplexer and Embedded Core/FPGA interface * 1:4 DEMUX * Low speed parallel Embedded Core/FPGA logic interface * Multi-channel alignment logic
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 6. Basic Logic Blocks, Receive Path, Single Channel (Typical Reference Clock Frequency)
CV_SELxx RWBIT9xx[3:0] MRWDxx[39:0]
40
2:1 MUX (x40)
SBYTSYNC_xx
For ORT42G5: xx = [AC, AD, BC, BD] x# = [A2, B2] For ORT82G5: xx = [AA, AB, ... BD] x# = [A1, ...B2]
4
Fibre Channel State Machine
SWDSYNC_xx
32-bit data 36 4 bits k-ctrl Synchronization Status bits RSYS_CLK_x# FIFO See Table 8 78.125 MHz 3
RWDxx[31:0]
32
10 SRBD_xx[0:9] 8B/10B
HDINP_xx
FPGA Logic
32-bit data 1:4 MultiRWBIT8xx[3:0] 4 DEMUX Channel 4 bits k-control (x 10) Alignment RALIGNxx[3:0] 4 Align Character Detect 78.125 MHz Clock
SCVxx
Encoder Byte 1:10 CML (with Align DEMUX Buffer bypass)
HDIN_xx
312.5 MHz Clocks 2
PLL XAUI State Machine DEMUX Block
CDR RX SERDES Block
RWCKxx
78.125 MHz
Multi-Channel Alignment Block
Backplane Serial Link
Logic Common to Block
REFCLKP_[A:B] RCK78[A:B]
78.125 MHz
MUX
From other channel or channels
To other channel or channels
{
REFCLK Buffer
From Control RCKSEL[0:1][A:B] Register
Each channel provides its own received clock, received data and K-character detect signals to the FPGA logic. Incoming data from multiple channels can be aligned using comma (/K/) characters or /A/ character (as specified either in Fibre Channel specifications or in IEEE 802.3ae for XAUI based interfaces). If the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in this 8b/10b bypass mode. Detailed descriptions of data synchronization, of the SERDES, DEMUX and Multi-Channel Alignment blocks and of the Fibre Channel and XAUI state machines are given in following sections. Receive clock distribution is described in a later section of this data sheet. Synchronization The SERDES RX logic performs four levels of synchronization on the incoming serial data stream. Each level builds upon the previous, providing first bit, then byte (character), then channel (32-bit word), and finally multi-channel alignment. Each step is described functionally in the following paragraphs. The details of the logical implementations are described in subsequent sections. Bit alignment is the task of the Clock/Data Recovery (CDR) block. This block utilizes a PLL that locks to the transitions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. If the PLL is unable to lock to the serial data stream, it instead locks to REFCLK[A:B] to stabilize the voltage-controlled oscillator (VCO), and periodically switches back to the serial data stream to again attempt synchronization. This process continues until a valid input data stream is detected and lock is achieved. The CDR can maintain lock on data as long as the input data stream contains an adequate data "eye" (i.e., jitter is within specification) and the maximum data stream run length is not exceeded.
{
REFCLKN_[A:B]
156.25 MHz
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit alignment times fall into two categories: realignment when the input serial data stream experiences an abrupt phase change (as may occur when protection switching is performed between two paths having different delays), and alignment from a no-signal condition. Realignment is very quick, since the PLL's VCO is already locked on frequency and only needs to adapt to the new phase. This re-alignment has been observed to require no more than one microsecond when REFCLK[A:B] = 156.25 MHz. Alignment from a no-signal condition has two components. First, there is the re-acquisition to the data's frequency and phase. The time required for re-acquisition to the data's frequency is minimized by logic that periodically switches the PLL to lock to the REFCLK[A:B] when it fails to lock on the serial data stream, thus limiting the VCO's frequency wander. Second, there is the time spent while the PLL is locking to REFCLK[A:B], which can be from zero to a maximum value, depending on when the serial data stream becomes valid in relation to the PLL's switching to/from REFCLK[A:B]. This alignment has been observed to require no more than 4 microseconds when REFCLK = 156.25 MHz. Byte alignment occurs once valid bit alignment is achieved. The byte aligner looks for a particular 7-bit sequence (either 0011111 or its complement, 1100000) that, in data that has been 8b/10b encoded per Fibre Channel or IEEE 802.3ae specifications, only occurs in the comma (/K/) characters K28.1, K28.5 and K28.7. Byte alignment only occurs when the ENBYSYNC_xx signal for that channel is active high, and re-alignment occurs on each 7-bit sequence encountered. However, if ENBYSYNC_xx is asserted active high and no comma character is encountered, and then is brought inactive low, the channel will still perform one byte alignment operation on the next comma character. Byte alignment occurs immediately when an alignment sequence is detected, so the lock time is only one clock period. Note: Each time the byte aligner performs an alignment, it also corrects the phase of the internal RBC_xx clock. This can result in the "stretching" of the clock by a half-phase in order to cause the output data to align with the rising edge of RBC_xx. Word (32-bit) alignment can occur after the Fibre Channel (XAUI_MODE_xx = 0) or XAUI (XAUI_MODE_xx = 1) state machine has reached the in-synchronization state. In Fibre Channel mode, synchronization (WDSYNC_xx = 1) will occur after three ordered sets of data have been received in the absence of any code violations. After this, the next ordered set will cause the output data to be aligned such that the comma character is in the most significant byte. Thus, 32-bit word alignment has been achieved when four ordered sets have been detected. The time required is directly dependent on comma-character density. Note: once word alignment is accomplished, no further alignment occurs unless and until WDSYNC_xx goes to zero and back to one again. Comma characters that are not located in the most significant byte position will not trigger further re-alignment while WDSYNC_xx is active. This behavior is as defined by the Fibre Channel specification. However, it means that, if the channel experiences an abrupt delay change (as could occur if an external MUX performs a protection switch between two links) and if the delay change is close enough to a full character or characters that not enough code violations are generated to cause loss of WDSYNC_xx, the channel could become misaligned and remain that way indefinitely. As mentioned above, this behavior is that defined by the Fibre Channel specification. In XAUI mode, as the state diagram later in this data sheet indicates, three error-free code-groups containing commas must be detected before synchronization is declared. Multi 2, 4 or 8 (ORT82G5 only) channel alignment (Lane alignment in XAUI mode) can be performed after 32bit word alignment is complete. Multi-channel alignment is described in later sections of this data sheet.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Receive CML Input Buffer and SERDES The receiver section receives high-speed serial data at its differential CML input port. The receive input is an ACcoupled input. The received data is sent to the clock recovery section which generates a recovered clock and retimes the data. Valid data will be received after the receive PLL has locked to the input data frequency and phase. The received serial data is converted to10-bit wide parallel data by the 1:10 demultiplexor. Clock recovery is performed by the SERDES block for each of the eight receive channels. This recovered data is then aligned to a 10-bit word boundary by detecting and aligning to a comma special character. Word alignment is done for either polarity of the comma character. The 10-bit code word is passed to the 8b/10b decoder, which provides an 8-bit byte of data, a special character indicator bit and a SBYTSYNC_xx signal (where again xx is a placeholder for AA,...,BD or AC, AD, BC, BD). Data from a SERDES channel is sent to the DEMUX block in 10-bit raw form or 8-bit decoded form across the SRBD_xx [9:0] port with a latency of approximately 14-23 cycles (bit periods of the incoming data). Accompanying this data are the comma-character indicator (SBYTSYNC_xx), link-state indicator (SWDSYNC_xx), clocks (SRBC0_xx, and SRBC1_xx), and code-violation indicator (SCVxx). The two internal clocks operated at twice the reference clock frequency. Figure 7 shows the receive path timing for a single SERDES channel. Figure 7. Receive Path Timing for a Single SERDES Channel
EMBEDDED CORE
1-bit HDIN[P:N]_xx pppp pppppp q 0123 456789 0
.....
.....
x y
r
2
r
3
r
4
r
5
r
6
r
7
r
8
r
9
sssss 01234
.....
LATENCY = APPROX 23 CYCLES SRBD_xx[9:0] p
10-bit SRBD_xx[9:0]
.....
p
q
r
s
t
z
SRBC0_xx SRBC1_xx SBYTSYNC_xx, SVCxx
..... ..... ..... .....
With the 8b10bR_xx control bit of the SERDES channel set to 1, the data presented at SRBD_xx[9:0] will be decoded characters. Bit 8 will indicate whether SRBDxx[7:0] represents an ordinary data character (bit 8 = 0), or whether SRBD_xx[7:0] represents a special character, like a comma. Bit 9 may be either a code violation indicator or one of seven out of synchronization state indicators, as described later. When 8b10bR is set to 0, the data at SRBD_xx[9:0] will not be decoded. The XAUI link-state machine should not be used in this mode of operation. When in XAUI mode, the MUX/DEMUX looks for /A/ (as defined in IEEE 802.3ae v.2.1) characters for channel alignment and requires the characters to be in decoded form for this to work 1:4 Demultiplexer (DEMUX) The1:4 DEMUX has to accumulate four sets of characters presented to it at the SERDES receive interface and put these out at one time at the low-speed receive interface. Another task of the 1:4 DEMUX is to recognize the synchronizing event and adjust the 4-byte boundary so that the synchronizing character leads off a new 4-byte word. In Fibre Channel mode, this synchronizing character is a comma. This feature will be referred to as DEMUX word alignment in other areas of this document. DEMUX word
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
alignment will only occur when the communication channel is synchronized. When there is no synchronization of the link, the 1:4 DEMUX will continue to output 4-byte words at some arbitrary, but constant, boundary. There are 2 control register bits available for each channel for word alignment. They are DOWDALGN_xx and NOWDALGN_xx. The DOWDALGN_xx bit is positive edge triggered. Writing a 0 followed by a 1 to this register bit will cause the corresponding DEMUX to look for a new comma character and align the 32-bit word such that the comma is in the most significant byte position. It is important that the comma is in the most significant byte position since the multi-channel aligner looks for comma in the most significant byte only. Typically, it is not necessary to set the DOWDALGN_xx bit. When the link state machine loses synchronization (DEMUXWAS_xx register bit is 0), the DEMUX block automatically looks for a new comma character irrespective of whether the DOWDALGN_xx bit is set or not. However, as discussed earlier, the comma character may become misaligned without the Fibre Channel link state machine indicating a loss of synchronization. In such cases, the DOWDALGN_xx bit must be toggled to force resynchronization. The NOWDALGN_xx bit is a level-sensitive bit. If it is a 1, then the DEMUX does not dynamically alter the word boundary based on comma and SWDSYNC_xx output of the SERDES. This might be useful if a channel were configured to bypass the multi-channel alignment FIFO and raw 40-bits of data are directed from SERDES to FPGA. In Fibre Channel mode, the default setting (NOWDALGN_xx = 0) causes the word boundary to be set as soon as the SERDES SWDSYNC_xx output is a 1 and a comma character has been detected. The character that is the comma becomes the most-significant portion of the demultiplexed word. When the SERDES loses link synchronization it will drop SWDSYNC_xx low. The DEMUX will begin search for word alignment as soon as SWDSYNC_xx goes to 1 again. The DEMUX passes on to the channel alignment FIFO block a set of control signals that indicate the location of the synchronizing event. RALIGN_xx[3:0] are these indicators. If there is no link synchronization, all of the RALIGN_xx[[3:0] bits will be zeros independent of synchronizing events that come in. When the link is synchronized, then the bit that corresponds to the time of the synchronization event will be set to a 1. The relationship between a time sequence of values input at SRBDxx[7:0] to the values output at RWD_xx[39:0] is shown in Figure 8. A parallel relationship exists between SRBDx[8] and RWBIT8_xx[3:0] as well as between SRBD_xx[9] and RWBIT9_xx[3:0].
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 8. Receive DEMUX Block for a Single SERDES Channel
10-bit SRBDxx[9:0] p q r s t x y z
LATENCY = 4 RSYS_CLK [A1,...,B2] CLOCKS RWD_xx[31:24] RWBIT8_xx[3] RWBIT9_xx[3] RWD_xx[23:16] RWBIT8_xx[2] RWBIT9_xx[2] RWD_xx[15:8] RWBIT8_xx[1] RWBIT9_xx[1] RWD_xx[7:0] RWBIT8_xx[0] RWBIT9_xx[0]
40-bit p pp 7-0 8 9 q qq 89 t t t
7-0
8
9
7-0
x
7-0
xx 89
r
7-0
r
8
r
9
y
7-0
yy 89 zz 89
s
7-0
ss 89
z
7-0
One clock per block of two or four channels, called RCK78[A,B], is sent to the FPGA. The control bits RCKSEL[A,B] are used to select the channel that is the source for these clocks.
Link State Machines
Two link state machines are included in the device, one for XAUI applications and a second for Fibre Channel applications. The Fibre Channel link state machine is responsible for establishing a valid link between the transmitter and the receiver and for maintaining link synchronization. The machine is initially in the Loss Of Synchronization (LOS) state upon power-on reset. This is indicated by WDSYNC_xx = 0. While in this state, the machine looks for a particular number of consecutive idle ordered sets without any invalid data transmission in between before declaring synchronization achieved. Achievement of synchronization is indicated by asserting WDSYNC_xx = 1. Specifically, the machine looks for three continuous idle ordered sets without any misaligned comma character or any running disparity based code violation in between. In the event of any such code violation, the machine would reset itself to the ground state and start its search for the idle ordered sets again. A typical valid sequence for achieving link synchronization would be K28.5 D21.4 D21.5 D21.5 repeated three times. In the synchronization achieved state, the machine constantly monitors the received data and looks for any kind of code violation that might result due to running disparity errors. If it were to receive four such consecutive invalid words, the link machine loses its synchronization and once again enters the loss of synchronization state (LOS). A pair of valid words received by the machine overcomes the effect of a previously encountered code violation. LOS is indicated by the status of WDSYNC_xx output which now transitions from 1 to 0. At this point the machine attempts to establish the link yet again. Figure 9 shows the state diagram for the Fibre Channel link state machine. LOS is also indicated by DEMUXWAS_xx status register bit. This bit is set to 0 during loss of synchronization.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 9. Fibre Channel Link State Machine State Diagram
LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1) VW CV a 2 VW OS CV h LOSS OF SYNCHRONIZATION (WDSYNC_XX = 0) OS CV g CV b 2 VW 1VW CV c 2 VW 1VW CV d 1VW
OS LOS = 1 f RST
LSM_ENABLE
e
+
POWERUP_RESET
OS LAST ORDERED SET RECEIVED: OS: IDLE ORDERED SET (A 4 CHARACTER BASED WORD HAVING COMMA AS THE 1ST CHARACTER) VW: VALID WORD (A 4 CHARACTER BASED WORD HAVING NO CODE VIOLATION) WITH AT LEAST TWO PRECEEDING VALID WORDS CV: CODE VIOLATION (RUNNING DISPARITY BASED ON ILLEGAL COMMA POSITION) 1VW: FIRST VALID WORD AFTER A CODE VIOLATION 2VW: SECOND VALID WORD AFTER A CODE VIOLATION
XAUI Link Synchronization Function
For each lane, the receive section of the XAUI link state machine incorporates a synchronization state machine that monitors the status of the 10-bit alignment. A 10-bit alignment is done in the SERDES based on a comma character such as K28.5. A comma (0011111 or its complement 1100000) is a unique pattern in the 10-bit space that cannot appear across the boundary between any two valid 10-bit code-groups. This property makes the comma useful for delimiting code-groups in a serial stream.This mechanism incorporates a hysteresis to prevent false synchronization and loss of synchronization due to infrequent bit errors. For each lane, the sync_complete signal is disabled until the lane achieves synchronization. The synchronization state diagram is shown in Figure 10. This state machine is modeled after draft IEEE 802.3ae, version 2.1 but will also operate with version 4.1 implementations. Table 4 and Table 5 describe the state variables used in Figure 10. The XAUI state machine does not have any control over the SERDES byte aligner. It is the user's responsibility to control the byte aligner through software access of register map addresses 30800 and 30900. Note that it takes four idle ordered sets (e.g. K28.5, Dxx.y, Dxx.y, Dxx.y) to bring the state machine from a loss_of_sync to a synch_acq'd_1 state. When back-to-back commas are used instead, it takes a total of five commas to achieve the same result as with idle ordered sets. Table 4. XAUI Link Synchronization State Diagram - Functions
Function sync_complete cg_comma cg_good cg_bad no_comma Description Indication that alignment code-group alignment has been established at the boundary indicated by the most recently received comma. Indication that a valid code-group, with correct running disparity, containing a comma has been received. Indication that a valid code-group with the correct running disparity has been received. Indication that an invalid code-group has been received. Indication that comma timer has expired. The timer is initialized upon receipt of a comma.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 5. XAUI Link Synchronization State Diagram Notation - Variables
Variable sync_status Description FAIL: Lane is not synchronized (correct 10-bit alignment has not been established). OK: Lane is synchronized. OK_NOC: Lane is synchronized but a comma character has not been detected in the past 200 code groups. TRUE: Align subsequent 10-bit words to the boundary indicated by the next received comma. FALSE: Maintain current 10-bit alignment. Current number of consecutive cg_good indications.
enable_CDET gd_cg
Figure 10. XAUI Link Synchronization State Diagram
reset
Loss_of_Sync sync_status <= FAIL enable_CDET <= TRUE sync_complete Comma_Detect_1 enable_CDET <= FALSE cg_bad cg_comma Comma_Detect_2
cg_bad
cg_comma Comma_Detect_3
cg_bad cg_comma
Sync_Acq'd_1 sync_status <= OK no_comma & cg_bad cg_bad Sync_ Acq'd_2 gd_cg <= 0 cg_good cg_bad Sync_ Acq'd_3 gd_cg <= 0 cg_good cg_bad Sync_ Acq'd_4 gd_cg <= 0 cg_good cg_bad cg_good x (gd_cg = 3) cg_good*(gd_cg=3) ~ no_comma & cg_bad
Sync_Acq'd_1a sync_status <= OK_NOC
cg_comma Sync_ Acq'd_2a gd_cg <= gd_cg + 1 cg_good x (gd_cg ! = 3) cg_bad cg_good x (gd_cg = 3) Sync_ Acq'd_3a gd_cg <= gd_cg + 1 cg_bad Sync_ Acq'd_4a gd_cg <= gd_cg + 1 cg_good x (gd_cg ! = 3) cg_bad cg_good x (gd_cg ! = 3)
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Multi-channel Alignment
The alignment FIFO allows the transfer of all data to the system clock. The Multi-Channel Alignment block (Figure 6) allows the system to be configured to allow the frame alignment of multiple slightly varying data streams. This optional alignment ensures that matching SERDES streams will arrive at the FPGA end in perfect data synchronization. Each channel is provided with a 24 word x 36-bit FIFO. The FIFO can perform two tasks: (1) to change the clock domain from receive clock to a clock from the FPGA side, and (2) to align the receive data over 2, 4, or 8 channels. This FIFO allows a timing budget of 230.4 ns that can be allocated to skew between the data lanes and for transfer to the system clock. The input to the FIFO consists of 36 bits of demultiplexed data, RALIGN_xx[3:0], RWD_xx[31:0], and RWBIT8_xx[3:0]. The four RALIGN_xx bits are control signals, and can be the alignment character detect signals indicating the presence of a comma character in Fibre Channel mode and the /A/ character in XAUI mode. The other 32 RWD_xx bits are the 8-bit data bytes from the 8b/10b decoder. The alignment character, if present, is the MSB of the data. The RWBIT8_xx indicates the presence of a Km.n control character in the receive data byte. Only RWBIT8_xx and RWD_xx inputs are stored in the FIFO. During alignment process, RALIGN[3]_xx is used to synchronize multiple channels. If a channel is not in any alignment group, it will set the FIFO-write-address to the beginning of the FIFO, and will set the FIFO-read-address to the middle of the FIFO, at the first assertion of RALIGN[3]_xx after reset or after the resync command. The RX_FIFO_MIN_xx register bits can be used to control the threshold for minimum unused buffer space in the alignment FIFOs between read and write pointers before overflow (OVFL) status is flagged. The synchronization algorithm consists of a down counter which starts to count down by 1 from its initial value of 18 (decimal) when an alignment character from any channel within an alignment group has been received. Once all the alignment characters within the alignment group have been received, the count is decremented by 2 until 0 is reached. Data is then read from the FIFOs and output to the FPGA. This algorithm is not repeated after multi-channel alignment has been achieved; resynchronization must be forced by toggling the appropriate FMPU_RESYNC bit.
ORT42G5 Multi-channel Alignment
The ORT42G5 has a total of four channels. The incoming data of these channels can be synchronized in two ways or they can be independent of one other. Two channels, C and D, within either SERDES block can be aligned together to form a pair, as shown in Figure 11. Alternately, all four channels can be aligned together to form a communication channel with a bandwidth of 10 Gbps, as shown in Figure 12. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. Figure 11. Dual Channel Alignment
Channel AC Channel AD Channel BC Channel BD Channel AC Channel AD Channel BC Channel BD
DUAL ALIGNMENT OF CHANNELS AC AND AD DUAL ALIGNMENT OF CHANNELS BC AND BD
t1 t0
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 12. Four Channel Alignment of SERDES Blocks A and B
Channel AC Channel AD Channel BC Channel BD Channel AC Channel AD Channel BC Channel BD
QUAD ALIGNMENT OF CHANNELS AC, AD, BC, AND BD
t0
ORT82G5 Multi-channel Alignment
The ORT82G5 has a total of eight channels (four per SERDES block). The incoming data of these channels can be synchronized in several ways or they can be independent of one other. Two channels within a SERDES block can be aligned together. Channel A and B and/or channel C and D can form a pair as shown in Figure 13. Alternately, all four channels of a SERDES block can be aligned together to form a communication channel with a bandwidth of 10 Gbps as shown in Figure 14. Finally, the alignment can be extended across both SERDES block to align all eight channels in ORT82G5 as shown in Figure 15. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. Figure 13. Dual Channel Alignment
Channel AA Channel AB Channel AC Channel AD Channel BA Channel BB Channel BC Channel BD Channel AA Channel AB Channel AC Channel AD Channel BA Channel BB Channel BC Channel BD
TWIN ALIGNMENT OF CHANNELS AA AND AB TWIN ALIGNMENT OF CHANNELS AC AND AD
TWIN ALIGNMENT OF CHANNELS BA AND BB TWIN ALIGNMENT OF CHANNELS BC AND BD
t3 t2 t1
t0
Figure 14. Alignment of SERDES Quads A and B
Channel AA Channel AB Channel AC Channel AD Channel BA Channel BB Channel BC Channel BD Channel AA Channel AB Channel AC Channel AD Channel BA Channel BB Channel BC Channel BD
QUAD ALIGNMENT OF CHANNELS AA, AB, AC, AND AD QUAD ALIGNMENT OF CHANNELS BA, BB, BC, AND BD
t0 t1
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 15. Alignment of all Eight SERDES Channels.
Channel AA Channel AB Channel AC Channel AD Channel BA Channel BB Channel BC Channel BD
Channel AA Channel AB Channel AC Channel AD Channel BA Channel BB Channel BC Channel BD
t0
Note that any channel within an alignment group can be removed from that alignment group by setting FMPU_STR_EN_xx to 0. The disabling of any channel(s) within an alignment group will not affect the operation of the remaining active channels. If the active channels are synchronized, that synchronization will be maintained and no data loss will occur. For every alignment group, there are both an OVFL and an OOS status register bit. The OVFL bit is set when alignment FIFO overflow occurs. The OOS bit is flagged when the down counter in the synchronization algorithm has reached a value of 0 and alignment characters from all channels within an alignment group have not been received. In the memory map section for the ORT42G5 the bits indicating OOS and OVFL are referred to as SYNC2_[A:B]_OOS and SYNC4_OOS and the bits indicating OVFL are SYNC2_[A:B]_OVFL and SYNC4_OVFL. In the memory map section for the ORT82G5, the bits indicating OOS and OVFL are referred to as SYNC2_[A1,A2,B1,B2]_OOS, SYNC4_[A:B]_OOS and SYNC8_OOS and the bits indicating OVFL are SYNC2_[A1,A2,B1,B2]_OVFL, SYNC4_[A:B]_OVFL and SYNC8_OVFL. Alignment can also be done between the receive channels on two ORT82G5 devices. Each of the two devices needs to provide its aligned K_CTRL or other alignment character to the other device, which will delay reading from a second alignment FIFO until all channels requesting alignment on the current device and all channels requesting alignment on the other device are aligned (as indicated on the K_CTRL character). These second alignment FIFOs will be implemented in FPGA logic on the ORT82G5. This scheme also requires that the reference clock for both devices be driven by the same signal.
XAUI Lane Alignment Function (Lane Deskew)
In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The mechanism restores the timing relationship between the 4 lanes by lining up the /A/ characters into a column. Figure 16 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies that at least 80 bits of skew compensation capability should be provided, which the devices significantly exceed.
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Lattice Semiconductor
Figure 16. Deskew Lanes by Aligning /A/ Columns
LANE 0 K R R K K R R R R K K K R R R A K K R R R A K K K R R K A K R
ORCA ORT42G5 and ORT82G5 Data Sheet
K R K K
R K
R R
K K R K R R K K R R K R K
LANE 1 LANE 2 K
R A R
K K
R
LANE 3
K
LANE 0 LANE 1 LANE 2 LANE 3
K K K K
R R R R
R R R R
K K K K
R R R R
K K K K
A A A A
R R R R
K K K K
K K K K
R R R R
K K K K
R R R R
R R R R
K K K K
Mixing Half-rate, Full-rate Modes
When channel alignment is enabled, all receive channels within an alignment group should be configured at the same rate. For example, in the ORT82G5 channels AA, AB, can be configured for twin alignment and full-rate mode, while channels AC, AD that form an alignment group can be configured for half-rate mode. In block alignment mode, each receive block can be configured in either half or full-rate mode. When channel alignment is disabled within a block, any receive channel within the block can be used in half-rate or full-rate mode. The clocking strategy for half-rate mode in both scenarios (channel alignment enabled or disabled) is described in the Reference Clocks and Internal Clock Distribution sections later in this data sheet.
Multi-channel Alignment Configuration
ORT42G5 Configuration
At startup, the legacy SERDES channel logic must be powered down and removed from any multi-channel alignment groups: * Setting bit 1 to one in registers at locations 30002, 30012, 30102, 30112, 30003, 30013, 30103 and 30113 powers down the legacy logic. (Note that the reset value for these bits is 0.) * Setting bits 4 and 5 to zero (reset condition) in the register at locations 30810 and 30910 removes the legacy logic from any alignment group. Register settings for multi-channel alignment are shown in Table 6. Table 6. Multichannel Alignment Modes
Register Bits FMPU_SYNMODE_[A:B][0:7] 00000000 00001010 00001111 Mode No multichannel alignment. Twin channel alignment. Four channel alignment.
To align two channels in SERDES A: * FMPU_SYNMODE_A = 00001010 (Register Location 30811) To align two channels in SERDES B: * FMPU_SYNMODE_B = 00001010 (Register Location 30911) To align all four channels: * FMPU_SYNMODE_A = 00001111 (Register Location 30811)
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
* FMPU_SYNMODE_B = 11111111 (Register Location 30911) To enable/disable multi-channel alignment of individual channels within a multi-channel alignment group: * FMPU_STR_EN_xx = 1 enabled * FMPU_STR_EN_xx = 0 disabled * (Register Location 30810 and 30910, where xx is one of AC, AD, BC or BD.) To resynchronize a multichannel alignment group set the following bit to zero, and then set it to one. * FMPU_RESYNC4 for four channels, AC, AD, BC and BD. (Register Location 30A02, bit 2) * FMPU_RESYNC2A for dual channels, AC and AD. (Register Location 30820, bit 5) * FMPU_RESYNC2B for block channels, BC and BD. (Register Location 30920, bit 5) To resynchronize an independent channel (resetting the write and the read pointer of the FIFO) set the following bit to zero, and then set it to one. FMPU_RESYNC1_xx (Register Locations 30820 and 30920, bits 2 and 3, where xx is one of AC, AD, BC or BD).
ORT82G5 Configuration
Register settings for multi-channel alignment are shown in Table 7. Table 7. Multi-channel Alignment Modes
Register Bits FMPU_SYNMODE_xx[0:1] 00 10 01 11 Mode No multi-channel alignment. Twin channel alignment. Quad channel alignment. Eight channel alignment.
Note: Where xx is one of A[A:D] and B[A:D].
To align all eight channels: * FMPU_SYNMODE_A[A:D] = 11 * FMPU_SYNMODE_B[A:D] = 11 To align all four channels in SERDES A: * FMPU_SYNMODE_A[A:D] = 01 To align two channels in SERDES A: * FMPU_SYNMODE_A[A:B] = 10 for channel AA and AB * FMPU_SYNMODE_A[C:D] = 10 for channel AC and AD A similar alignment can be defined for SERDES B. To enable/disable synchronization signal of individual channel within a multi-channel alignment group: * FMPU_STR_EN_xx = 1 enabled * FMPU_STR_EN_xx = 0 disabled where xx is one of A[A:D] and B[A:D]. To resynchronize a multi-channel alignment group set the following bit to zero, and then set it to one: * FMPU_RESYNC8 for eight channel A[A:D] and B[A:D] * FMPU_RESYNC4A for quad channel A[A:D] * FMPU_RESYNC2A1 for twin channel A[A:B] 31
Lattice Semiconductor
* * * * FMPU_RESYNC2A2 for twin channel A[C:D] FMPU_RESYNC4B for quad channel B[A:D] FMPU_RESYNC2B1 for twin channel B[A:B] FMPU_RESYNC2B2 for twin channel B[C:D]
ORCA ORT42G5 and ORT82G5 Data Sheet
To resynchronize an independent channel (resetting the write and the read pointer of the FIFO) set the following bit to zero, and then set it to one: * FMPU_RESYNC1_xx
ORT42G5 Alignment Sequence
1. Follow steps 1, 2 and 3 in the start up sequence described in a later section. 2. Initiate a SERDES software reset by setting the SWRST bit to 1 and then to 0. Note that, any changes to the SERDES configuration bits should be followed by a software reset. 3. Wait for 3 ms. REFCLK should be toggling by this time. During this time, configure the following registers. Set the following bits in registers 30820, 30920: * XAUI_MODE_xx-set to 1 for XAUI mode or keep the default value of 0 if the Fibre Channel state machine was selected. * Enable channel alignment by setting FMPU_SYNMODE bits in registers 30811, 30911. * FMPU_SYNMODE_xx. Set to appropriate values for 2 or 4 channel alignment based on Table 6. * Set RCLKSEL[A:B] and TCKSEL[A:B] bits in register 30A00. * RCKSEL[A:B]-choose clock source for 78 MHz RCK78x (Table 18). * TCKSEL[A:B]-Choose clock source for 78 MHz TCK78x (Table 17). Send data on serial links. Monitor the following status/alarm bits: * Monitor the following alarm bits in registers 30020, 30030, 30120, 30130. * LKI-PLL_xx lock indicator. A 1 indicates that PLL has achieved lock. * Monitor the following status bits in registers 30804, 30904 * XAUISTAT_xx - In XAUI mode, they should be 10. Monitor the following status bits in registers 30805, 30905 * DEMUXWAS_xx - They should be 1 indicating word alignment is achieved. * CH24_SYNCxx - They should be 1 indicating channel alignment. This is cleared by resync. 4. Write a 1 to the appropriate resync registers 30820, 30920 or 30A02. Note that this assumes that the previous value of the resync bits are 0. The resync operation requires a rising edge. Two writes are required to the resync bits: write a 0 and then write a 1. It is highly recommended to precede a resync with a word alignment, especially in situations where a disturbance in the receive SERDES path can cause misalignment of data and OOS indications without bringing the FC/XAUI state machine to a loss of synch state. A word alignment is achieved by writing a 0 and then a 1 to the appropriate DOWDALIGNxx bits in registers 30810/30910. Check out-of-sync and FIFO overflow status in registers 30814 (Bank A). * SYNC2_A_OOS, SYNC2_A_OVFL - by 2 alignment. Check out-of-sync status in registers 30914 (Bank B). * SYNC2_B_OOS, SYNC2_B_OVFL - by 2 alignment. Check out-of-sync status in registers 30A03. * SYNC4_OOS, SYNC4_OVFL - by 4 alignment. * If out-of-sync bit is 1, then rewrite a 1 to the appropriate resync registers and monitor the OOS bit again. * If Out of Synchronization (OOS) bit is 0 but OVFL bit is 1, then check if the RX_FIFO_MIN value has been pro32
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
grammed to a value > 0. (Default value is 0.) Change the value to 0 and check the OVFL bit again. If OOS and OVFL are 1, then rewrite a 1 to the appropriate resync registers. The resync operation requires a rising edge. Two writes are required to the resync bits: write a 0 and then write a 1.
ORT82G5 Alignment Sequence
1. Follow steps 1 and 2 in the start-up sequence described in a later section. 2. Initiate a SERDES software reset by setting the SWRST bit to 1 and then to 0. Note that any changes to the SERDES configuration bits should be followed by a software reset. 3. Wait for 3 ms. REFCLK should be toggling by this time. During this time, configure the following registers. Set the following bits in registers 30820, 30920 * XAUI_MODE_xx-set to 1 for XAUI mode or keep the default value of 0 if the Fibre Channel state machine was selected. * Enable channel alignment by setting FMPU_SYNMODE bits in registers 30811, 30911. * FMPU_SYNMODE_xx. Set to appropriate values for 2, 4, or 8 alignment based on Table 7. * Set RCLKSEL[A:B] and TCKSEL[A:B] bits in registers 30A00. * RCKSEL[A:B] - Choose clock source for 78 MHz RCK78x (Table 18). * TCKSEL[A:B] - Choose clock source for 78 MHz TCK78x (Table 17). Send data on serial links. Monitor the following status/alarm bits: * Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130. * LKI-PLL_xx lock indicator. A 1 indicates that PLL has achieved lock. Monitor the following status bits in registers 30804, 30904: * XAUISTAT_xx - In XAUI mode, they should be 10. Monitor the following status bits in registers 30805, 30905 * DEMUXWAS_xx-They should be 1 indicating word alignment is achieved. * CH248_SYNCxx-They should be 1 indicating channel alignment. This is cleared by resync. 4. Write a 1 to the appropriate resync registers 30820, 30920 or 30A02. Note that this assumes that the previous value of the resync bits are 0. The resync operation requires a rising edge. Two writes are required to the resync bits: write a 0 and then write a 1. It is highly recommended to precede a resync with a word alignment, especially in situations where a disturbance in the receive SERDES path can cause misalignment of data and OOS indications without bringing the FC/XAUI state machine to a loss of synch state. A word alignment is achieved by writing a 0 and then a 1 to the appropriate DOWDALIGNxx bits in registers 30810/30910. Check out-of-sync and FIFO overflow status in registers 30814 (Bank A). * SYNC4_A_OOS, SYNC4_A_OVFL-by 4 alignment. * SYNC2_A2_OOS, SYNC_A2_OVFL or SYNC2_A1_OOS, SYNC2_A1_OVFL-by 2 alignment. * Check out-of-sync status in registers 30914 (Bank B). * SYNC4_B_OOS, SYNC4_B_OVFL-by 4 alignment. * SYNC_B2_OOS, SYNC2_B2_OVFL or SYNC2_B1_OOS, SYNC_B1_OVFL-by 2 alignment. * Check out-of-sync status in register 30A03 * SYNC8_OOS, SYNC8_OVFL-by 8 alignment. * If out-of-sync bit is 1, then rewrite a 1 to the appropriate resync registers and monitor the OOS bit again. If Out of Synchronization (OOS) bit is 0 but OVFL bit is 1, then check if the RX_FIFO_MIN value has been programmed to a value > 0. (Default value is 0.) Change the value to 0 and check the OVFL bit again. If OOS and OVFL are 1, then rewrite a 1 to the appropriate resync registers. The resync operation requires a rising edge. Two writes are required to the resync bits: write a 0 and then write a 1. 33
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Embedded Core/FPGA Interface This block provides the data formatting and receive data and clock signal transfers between the Embedded Core and the FPGA Logic. There are also control and status registers in the FPGA portion of the chip which contain bits to control the receive logic and to record status. These are described in later sections of this data sheet and communicate with the core using the System Bus. The demultiplexed, receive word outputs to the FPGA are shown in Figure 6. These are each 40 bits wide. There are eight of these interfaces, one for each SERDES channel. Each consist of four groups of 10-bit data or four groups of decoded information depending on setting of 8b10bR_xx control register bits. Each 10-bit group of decoded information includes 8 bits of data and a 1 bit K_CTRL indicator derived from the received data and a tenth bit of status information. The function of the tenth bit varies from group to group and includes code violation, Out of Synchronization (OOS) indicators and the CH24_SYNC24_xx and CH248_SYNC_xx status bits. CH24_SYNC or CH248_SYNC_xx indicates the status of multi-channel alignment of channel xx and are high when the count for the multi-channel alignment block reaches zero regardless of whether or not multi-channel alignment is successful. The mapping of the 10-bit groups to the MRWD_xx[39:0] bits output to the FPGA logic is summarized in Table 8. The various functions of the bits that vary from channel to channel, i.e., bits 29 and 19, are also described in Table 9 and Table 10. Table 8. Definition of Bits of MRWDxx[39:0]
8b10bR=0 Bit Index 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 NOCHALGN[A:B]=1 CV_SELxx=0 bit 9 of 10-bit data 3 bit 8 of 10-bit data 3 bit 7 of 10-bit data 3 bit 6 of 10-bit data 3 bit 5 of 10-bit data 3 bit 4 of 10-bit data 3 bit 3 of 10-bit data 3 bit 2 of 10-bit data 3 bit 1of 10-bit data 3 bit 0 of 10-bit data 3 bit 9 of 10-bit data 2 bit 8 of 10-bit data 2 bit 7 of 10-bit data 2 bit 6 of 10-bit data 2 bit 5 of 10-bit data 2 bit 4 of 10-bit data 2 bit 3 of 10-bit data 2 bit 2 of 10-bit data 2 bit 1 of 10-bit data 2 bit 0 of 10-bit data 2 bit 9 of 10-bit data 1 bit 8 of 10-bit data 1 bit 7 of 10-bit data 1 bit 6 of 10-bit data 1 bit 5 of 10-bit data 1 bit 4 of 10-bit data 1 bit 3 of 10-bit data 1 8b10bR=1 NOCHALGN[A:B]=1 CV_SELxx=1 CV_xx3, code violation, byte 3 K_CTRL for byte 3 bit 7 of byte3 bit 6 of byte 3 bit 5 of byte 3 bit 4 of byte 3 bit 3 of byte 3 bit 2 of byte 3 bit 1 of byte 3 bit 0 of byte 3 CV_xx2, code violation, byte 2 K_CTRL for byte 2 bit 7 of byte 2 bit 6 of byte 2 bit 5 of byte 2 bit 4 of byte 2 bit 3 of byte 2 bit 2 of byte 2 bit 1 of byte 2 bit 0 of byte 2 CV_xx1, code violation, byte 1 K_CTRL for byte 1 bit 7 of byte 1 bit 6 of byte 1 bit 5 of byte 1 bit 4 of byte 1 bit 3 of byte 1 NOCHALGN[A:B]=0 CV_SELxx=1 See Table 9 and Table 10 K_CTRL for byte 3 bit 7 of byte3 bit 6 of byte 3 bit 5 of byte 3 bit 4 of byte 3 bit 3 of byte 3 bit 2 of byte 3 bit 1 of byte 3 bit 0 of byte 3 See Table 9 and Table 10 K_CTRL for byte 2 bit 7 of byte 2 bit 6 of byte 2 bit 5 of byte 2 bit 4 of byte 2 bit 3 of byte 2 bit 2 of byte 2 bit 1 of byte 2 bit 0 of byte 2 See Table 9 and Table 10 K_CTRL for byte 1 bit 7 of byte 1 bit 6 of byte 1 bit 5 of byte 1 bit 4 of byte 1 bit 3 of byte 1
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Lattice Semiconductor
Table 8. Definition of Bits of MRWDxx[39:0] (Continued)
8b10bR=0 Bit Index 12 11 10 09 08 07 06 05 04 03 02 01 00 NOCHALGN[A:B]=1 CV_SELxx=0 bit 2 of 10-bit data 1 bit 1 of 10-bit data 1 bit 0 of 10-bit data 1 bit 9 of 10-bit data 0 bit 8 of 10-bit data 0 bit 7 of 10-bit data 0 bit 6 of 10-bit data 0 bit 5 of 10-bit data 0 bit 4 of 10-bit data 0 bit 3 of 10-bit data 0 bit 2 of 10-bit data 0 bit 1 of 10-bit data 0 bit 0 of 10-bit data 0
ORCA ORT42G5 and ORT82G5 Data Sheet
8b10bR=1 NOCHALGN[A:B]=1 CV_SELxx=1 bit 2 of byte 1 bit 1 of byte 1 bit 0 of byte 1 CV_xx0, code violation, byte 0 K_CTRL for byte 0 bit 7 of byte 0 bit 6 of byte 0 bit 5 of byte 0 bit 4 of byte 0 bit 3 of byte 0 bit 2 of byte 0 bit 1 of byte 0 bit 0 of byte 0 NOCHALGN[A:B]=0 CV_SELxx=1 bit 2 of byte 1 bit 1 of byte 1 bit 0 of byte 1 VL (connected to ground) K_CTRL for byte 0 bit 7 of byte 0 bit 6 of byte 0 bit 5 of byte 0 bit 4 of byte 0 bit 3 of byte 0 bit 2 of byte 0 bit 1 of byte 0 bit 0 of byte 0
Table 9. Definition of Status Bits of MRWDxx that Vary for Different Channels for the ORT42G5
Channel Index all AC AC AD AD BC BC BD BD Bit Index 39 29 19 29 19 29 19 29 19 Name CH24_SYNCxx CV_AC_OR SYNC2_A_OOS CV_AD_OR SYNC4_OOS CV_BC_OR SYNC2_B_OOS CV_BD_OR SYNC4_OOS Description Multi-channel alignment attempt complete if 1 Code violation in one or more of the received 10-bit groups for channel AC Dual channel synchronization of channels AC and AD not successful if 1 Code violation in one or more of the received 10-bit groups for channel AD Four channel synchronization not successful if 1 Code violation in one or more of the received 10-bit groups for channel BC Dual channel synchronization of channels BC and BD not successful if 1 Code violation in one or more of the received 10-bit groups for channel BD Eight channel synchronization not successful if 1
In the ORT42G5, SYNC2_[A, B]_OOS and SYNC4_OOS signals can be used with CH24_SYNC_xx to determine if the desired multi-channel alignment was successful. If, when CH24_SYNC_xx goes high with the corresponding OOS signal remaining low, the data being transferred across the core/FPGA interface is correctly aligned between channels. Note that only the signals corresponding to the selected alignment mode will be meaningful. Table 10. Definition of Status Bits of MRWDxx that Vary for Different Channels for the ORT82G5
Channel Index all AA AA AB AB AC AC AD AD Bit Index 39 29 19 29 19 29 19 29 19 Name CH248_SYNCxx CV_AA_OR SYNC2_A1_OOS CV_AB_OR SYNC4_A_OOS CV_AC_OR SYNC2_A2_OOS CV_AD_OR SYNC8_OOS Description Multi-channel alignment attempt complete if 1 Code violation in one or more of the received 10-bit groups for channel AA Dual channel synchronization of channels AA and AB not successful if 1 Code violation in one or more of the received 10-bit groups for channel AB Quad channel synchronization of SERDES quad A not successful if 1 Code violation in one or more of the received 10-bit groups for channel AC Dual channel synchronization of channels AC and AD not successful if 1 Code violation in one or more of the received 10-bit groups for channel AD Eight channel synchronization not successful if 1
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 10. Definition of Status Bits of MRWDxx that Vary for Different Channels for the ORT82G5 (Continued)
Channel Index BA BA BB BB BC BC BD BD Bit Index 29 19 29 19 29 19 29 19 Name CV_BA_OR SYNC2_B1_OOS CV_BB_OR SYNC4_B_OOS CV_BC_OR SYNC2_B2_OOS CV_BD_OR SYNC8_OOS Description Code violation in one or more of the received 10-bit groups for channel BA Dual channel synchronization of channels BA and BB not successful if 1 Code violation in one or more of the received 10-bit groups for channel BB Quad channel synchronization of SERDES quad B not successful if 1 Code violation in one or more of the received 10-bit groups for channel BC Dual channel synchronization of channels BC and BD not successful if 1 Code violation in one or more of the received 10-bit groups for channel BD Eight channel synchronization not successful if 1
For the ORT82G5, the SYNC2_[A1,A2,B1,B2]_OOS, SYNC4_[A:B]_OOS,and SYNC8_OOS signals can be used with CH248_SYNC_xx to determine if the desired multi-channel alignment was successful. If, when CH248_SYNC_xx goes high the corresponding OOS signal remains low, the data being transferred across the core/FPGA interface is correctly aligned between channels. Note that only the signals corresponding to the selected alignment mode will be meaningful. For both devices, the code violation signals will only be valid if the corresponding CV_SELxx = 1. (If 8b10bR=0, CV_SEL should also be zero. The CV_xx_OR signals are obtained by ORing four code violation signals from the 1:4 DEMUX block. These are primarily indicators of received signal quality since a single code violation will not force a loss of sync (LOS) state in the word alignment state machines. Since these signals come from the DEMUX block, if multi-channel alignment is enabled, the code violation signals correspond to data that must still be multichannel aligned. Hence these signals provide advance notification of detected violations in data that will appear at the core/FPGA interface several clock cycles later. The exact number of clock cycles that the data is delayed depends on the skew between the incoming data for the different channels. Transceiver FPGA/Embedded Core Signals Table 12 summarizes the interface signals between the FPGA logic and the core. In the table, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out of the embedded core. Table 11. Transceiver Embedded Core/FPGA Interface Signal Description for the ORT42G5
FPGA/Embedded Core Interface Signal Name (xx = [AC, AD, BC or BD]) Transmit Path Signals TWDxx[31:0] TCOMMAxx[3:0] TBIT9xx[3:0] TSYS_CLK_xx TCK78[A:B] Receive Path Signals MRWDxx[39:0] RWCKxx RCK78[A:B] RSYS_CLK_A2 RSYS_CLK_B2 CV_SELxx SYS_RST_N O O O I I I I Receive data - Channel xx (see Table 8 and Table 9). Low-speed receive clock--Channel xx. Receive low-speed clock to FPGA--SERDES Quad [A:B]. Low-speed receive FIFO clock for channels AC, AD Low-speed receive FIFO clock for channels BC, BD Enable detection of code violations in the incoming data Synchronous reset of the channel alignment blocks. I I I I O Transmit data - channel xx. Transmit comma character - channel xx. Transmit force negative disparity - channel xx Transmit low-speed clock to the FPGA - channel xx Transmit low-speed clock to the FPGA - SERDES Quad [A:B]. Input (I) to or Output (O) from Core
Signal Description
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 12. Transceiver Embedded Core/FPGA Interface Signal Description for the ORT82G5
FPGA/Embedded Core Interface Signal Name xx=... line remain (xx = [AA, ..., BD] Transmit Path Signals TWDxx[31:0] TCOMMAxx[3:0] TBIT9xx[3:0] TSYS_CLK_xx TCK78[A:B] Receive Path Signals MRWDxx[39:0] RWCKxx RCK78[A:B] RSYS_CLK_A1 RSYS_CLK_A2 RSYS_CLK_B1 RSYS_CLK_B2 CV_SELxx SYS_RST_N O O O I I I I I I Receive data - Channel xx (see Table 8 and Table ). Low-speed receive clock--Channel xx. Receive low-speed clock to FPGA--SERDES Quad [A:B]. Low-speed receive FIFO clock for channels AA, AB Low-speed receive FIFO clock for channels AC, AD Low-speed receive FIFO clock for channels BA, BB Low-speed receive FIFO clock for channels BC, BD Enable detection of code violations in the incoming data Synchronous reset of the channel alignment blocks. I I I I O Transmit data - channel xx. Transmit comma character - channel xx. Transmit force negative disparity - channel xx Transmit low-speed clock to the FPGA - channel xx Transmit low-speed clock to the FPGA - SERDES Quad [A:B]. Input (I) to or Output (O) from Core
Signal Description
Reference Clocks and Internal Clock Distribution
Reference Clock Requirements
There are two pairs of reference clock inputs on the ORT42G5 and ORT82G5. The differential reference clock is distributed to all channels in a block. Each channel has a differential buffer to isolate the clock from the other channels. The input clock is preferably a differential signal; however, the device can operate with a single-ended input. The input reference clock directly impacts the transmit data eye, so the clock should have low jitter. In particular, jitter components in the DC to 5 MHz range should be minimized. The required electrical characteristics for the reference clock are given in Table 38. Note: In sections of this data sheet, the differential clocks are simply referred to as the reference clock as REFCLK_[A:B].
Synthesized and Recovered Clocks
The SERDES Embedded Core block contains its own dedicated PLLs for transmit and receive clock generation. The user provides a reference clock of the appropriate frequency, as described in the previous section. The transmitter PLL uses the REFCLK_[A,B] inputs to synthesize the internal high-speed serial bit clocks. The receiver PLLs extract the clock from the serial input data and retime the data with the recovered clock. The receive PLL for each channel has two modes of operation - lock to reference and lock to data with retiming. When no data or invalid data is present on the HDINP_xx and HDINN_xx pins, the receive VCO will not lock to data and its frequency can drift outside of the nominal 350 ppm range. Under this condition, the receive PLL will lock to REFCLK_[A,B] for a fixed time interval and then will attempt to lock to receive data. The process of attempting to lock to data, then locking to clock will repeat until valid input data exists. There is also a control register bit per channel to force the receive PLL to always lock to the reference clock. The high-speed transmit and receive serial data links can run at 0.6 to 3.7 Gbps, depending on the frequency of the reference clock and the state of the control bits from the internal transmit control register. The interface to the serializer/deserializer block runs at 1/10th the bit rate of the data lane. Additionally, the MUX/DEMUX logic converts the
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
data rate and bit-width so the FPGA core can run at 1/4th this frequency which gives a range of 15 to 92.5 MHz for the data in and out of the FPGA.
Internal Clock Signals at the FPGA/Core Interface for the ORT42G5
There are several clock signals defined at the FPGA/Embedded Core interface in addition to the external reference clock for each SERDES block. All of the ORT42G5 clock signals are shown in Figure 17 and are described following the figure. Figure 17. ORT42G5 Clock Signals (High Speed Serial I/O Also Shown)
RCK78A TCK78A RSYS_CLK_A2 RWCKAC TSYS_CLK_AC RWCKAC TSYS_CLK_AD 2 REFCLK[P:N]_A
Common Logic, Block A
2 HDIN[P:N]_AC HDOUT[P:N]_AC HDIN[P:N]_AD HDOUT[P:N]_AD
Channel AC
2 2
Channel AD
2
FPGA Logic
RCK78B TCK78B RSYS_CLK_B2 RWCKBC TSYS_CLK_BC RWCKBD TSYS_CLK_BD 2 REFCLK[P:N]_B
Backplane Serial Link
Common Logic, Block B
2 HDIN[P:N]_BC HDOUT[P:N]_BC HDIN[P:N]_BD
Channel BC Channel BD
2 2 2
HDOUT[P:N]_BD
REFCLKP_[A:B], REFCLKN_[A:B]: These are the differential reference clocks provided to the ORT42G5 device as described earlier. They are used as the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbps, the reference clocks will be at a frequency of 156.25 MHz. RWCK[AC, AD, BC, BD]: These are the low-speed receive clocks from the embedded core to the FPGA across the core-FPGA interface. These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCKAC belongs to Channel AC, RWCKBC belongs to channel BC and so on. With a reference clock input of 156.25 MHz, these clocks operate at 78.125 MHz. RCK78[A:B]: These are muxed outputs of RWCKA[C or D] and RWCKB[C or D] respectively. With a reference clock input of 156.25 MHz, these clocks operate at 78.125 MHz. RSYS_CLK_[A:B]2 These clocks are inputs to the SERDES blocks A and B respectively from the FPGA. These are used by each channel as the read clock to read received data from the alignment FIFO within the embedded core. Clock RSYS_CLK_A2 is used by channels in the SERDES block A and RSYS_CLK_B2 by channels in the SERDES block B. To guarantee that there is no overflow in the alignment FIFO, it is an absolute requirement that the write and read clocks be frequency locked within 0 ppm. Examples of how to achieve this are shown in the later section on recommended board-level clocking.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
TCK78[A:B]: This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the 2 transmit SERDES clocks per block operating at up to 92.5 MHz in the embedded core. There is one clock output per SERDES block. TSYS_CLK[AC, AD, BC, BD]: These clocks are inputs to the SERDES block A and B respectively from the FPGA. These are used by each channel to control the timing of the Transmit Data Path. To guarantee correct transmit operation theses clocks must be frequency locked within 0 ppm to TCK78[A:B].
Transmit and Receive Clock Rates
Table 13 shows typical relationship between the data rates, the reference clock, the transmit TCK78[A:B] clock and the receive RCK78[A:B] clock. The selection of full-rate or half-rate for a given reference clock speed is set by bits in the transmit and receive control registers and can be set per channel. Table 13. Transmit Data and Clock Rates
TCK78[A: B] and RCK78[A:B] Clocks 15 MHz 25 MHz 31.25 MHz 50 MHz 62.5 MHz 78 MHz 92.5 MHz Rate of Channel Selected as Clock Source Half Half Half Full Full Full Full
Data Rate 0.6 Gbps 1.0 Gbps 1.25 Gbps 2.0 Gbps 2.5 Gbps 3.125 Gbps 3.7 Gbps
Reference Clock 60 MHz 100 MHz 125 MHz 100 MHz 125 MHz 156 MHz 185 MHz
Besides taking in a TSYS_CLK_xx from the FPGA logic for each channel, the transmit path logic sends back a clock of the same frequency, but arbitrary phase. This clock, TCK78[A:B], is derived from the MUX block of one of the 2 channels in its SERDES block. The MUX blocks provide the potential source for TCK78[A:B] by a divide-by-4 of the SERDES STBC311xs clock used in synchronizing the transmit data words in the STBC311xx clock domain. The STBC311xx clocks are internal to the core and are not brought across the core/FPGA interface The receiver section receives high-speed serial data at its differential CML input port and sends in to the Clock and Data Recovery (CDR) block. The CDR block then generates a recovered clock (RWCKxx) and retimes the data. Thus, the recovered receive clocks are asynchronous between channels.
Transmit Clock Source Selection
The TCKSEL[A:B] bit select the source channel of TCK78[A:B]. The selection of the source for TCK78[A:B] is controlled by this bit as shown in Table 14. Table 14. TCK78[A:B] Source Selection
TCKSEL[A:B] 0 1 Clock Source Channel C Channel D
Recommended Transmit Clock Distribution for the ORT42G5
As an example of the recommended clock distribution approach, TSYS_CLK_A[C or D] can be sourced by TCK78A as shown in Figure 18 if the transmit line rate are common for both channels in a block. Similar clocking would be used for Block B.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 18. Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
TCK78A
Common Logic, Block A Channel AC
2
REFCLK[P:N]_A
FPGA Logic
156.25 MHz
TSYS_CLK_AC
TSYS_CLK_AD
Channel AD
Two Channels of 3.125 Gbps Outgoing Serial Data
All Clocks at 78.125 MHz
If the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in Figure 19 can be used. The figure shows TSYS_CLK_AC being sourced by TCK78A and TSYS_CLK_AD being sourced by TCK78A/2 (the division is done in FPGA logic). Similar clocking would be used for Block B. Figure 19. Mixed Rate Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
50 MHz Channel AC Selected as Clock Source TCK78A TSYS_CLK_AC
Common Logic, Block A Channel AC
2
REFCLK[P:N]_A
FPGA Logic
100 MHz
/2
TSYS_CLK_AD 25 MHz
Channel AD
One Channel of 2.0 Gbps (Full-Rate) and One Channel of 1.0 Gbps (Half-Rate) Outgoing Serial Data
Receive Clock Source Selection and Recommended Clock Distribution In the receive path, one clock per block of two channels, called RCK78[A:B], is sent to the FPGA logic. The control register bits RCKSEL[A:B] is used to select the clock source for these clocks. The selection of the source for RCK78[A:B] is controlled by this bit as shown in Table 15. Table 15. RCK78[A:B] Source Selection
RCKSEL[A:B] 0 1 Clock Source Channel C Channel D
In the receive channel alignment bypass mode the data and recovered clocks for the four channels are independent. The data for each channel are synchronized to the recovered clock from that channel. Figure 21 shows the recommended receive clocking for a single block.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 20. Receive Clocking for a Single Block (Similar Connections Would Be Used for Block B)
78.125 MHz RCK78A RSYS_CLK_A2
Common Logic, Block A
2
REFCLK[P:N]_A
FPGA Logic
All Recovered Clocks at 78.125 MHz
156.25 MHz Channel AC Channel AD Two Channels of 3.125 Gbps Incoming Serial Data
RWCKAC
RWCKAD
The receive channel alignment bypass mode allows mixing of half and full line rates among the channels, as shown in Figure 21. The figure shows channel AC configured in full rate mode at 2.0 Gbps. Channel AD configured in halfrate mode at 1.0 Gbps. The receive alignment FIFO per channel cannot be used in this mode. Figure 21. Receive Clocking for Mixed Line Rates
25 MHz or 50 MHz RCK78A RSYS_CLK_A2 RWCKAC
Common Logic, Block A
2
REFCLK[P:N]_A
100 MHz Channel AC One Channel of 2.0 Gbps (Full-Rate) and One Channel of 1.0 Gbps (Half-Rate) Incoming Serial Data
50 MHz 25 MHz
RWCKAD
FPGA Logic
Channel AD
Each SERDES block can also be configured for any line rate (0.6 to 3.7 Gbps), since each block has its own reference clock input pins.
Multi-Channel Alignment Clocking Strategies for the ORT42G5
The data on the four channels in the ORT42G5 can be independent of each other or can be synchronized in two different ways. For example, two channels within a SERDES block can be aligned together, channel C and channel D. Alternatively, all four channels in a SERDES block can be aligned together to form a communication channel with a bandwidth of 10 Gbps. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. Clocking strategies for these various modes are described in the following paragraphs. For dual alignment both channels must be sourced by the same clock. Either RWCKAC or RWCKAD can be connected to RSYS_CLK_A2. A clocking example for dual alignment is shown in Figure 22.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 22. Receive Clocking for a Dual Alignment in a Single Block (Similar Connections Would Be Used for Block B)
RCK78A TCK78A RSYS_CLK_A2
Common Logic, Block A
2
REFCLK[P:N]_A
FPGA Logic
156.25 MHz Channel AC Two Bidirectional Channels of 3.125 Gbps Serial Data Channel AD
RWCKAC TSYS_CLK_AC RWCKAD TSYS_CLK_AD
All Clocks at 78.125 MHz
For quad alignment, either RCK78A or RCK78B can be used to source RSYS_CLK_[A:B]2 as shown in Figure 23. Figure 23. Clocking for Quad Alignment
RCK78A TCK78A RSYS_CLK_A2 RWCKAC TSYS_CLK_AC RWCKAD TSYS_CLK_AD REFCLK[P:N]_A 2
Common Logic, Block A
156.25 MHz
Channel AC
Channel AD Four Bidirectional Channels of 3.125 Gbps Serial Data
FPGA Logic
RCK78B TCK78B RSYS_CLK_B2 RWCKBC TSYS_CLK_BC RWCKBD TSYS_CLK_BD
Common Logic, Block B
2 REFCLK[P:N]_B
Channel BC Channel BD
All Clocks at 78.125 MHz
42
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Internal Clock Signals at the FPGA/Core Interface for the ORT82G5
There are several clock signals defined at the FPGA/Embedded Core interface in addition to the external reference clock for each SERDES quad. All of the ORT82G5 clock signals are shown in Figure 24 and are described following the figure. Figure 24. ORT82G5 Clock Signals (High Speed Serial I/O Also Shown)
RCK78A TCK78A RWCKAA RSYS_CLK_A1 TSYS_CLK_AA RWCKAB
Common Logic, Quad A Channel AA
2 2 2 2
REFCLK[P:N]_A HDIN[P:N]_AA HDOUT[P:N]_AA HDIN[P:N]_AB HDOUT[P:N]_AB HDIN[P:N]_AC HDOUT[P:N]_AC HDIN[P:N]_AD HDOUT[P:N]_AD
Channel AB
TSYS_CLK_AB RWCKAC
2 2
Channel AC
TSYS_CLK_AC RWCKAD RSYS_CLK_A2 TSYS_CLK_AD RCK78B TCK78B RWCKBA RSYS_CLK_B1 TSYS_CLK_BA RWCKBB
2 2 2 2 2
Channel AD
FPGA Logic
Common Logic, Quad B Channel BA
REFCLK[P:N]_B HDIN[P:N]_BA HDOUT[P:N]_BA HDIN[P:N]_BB HDOUT[P:N]_BB HDIN[P:N]_BC HDOUT[P:N]_BC HDIN[P:N]_BD HDOUT[P:N]_BD
Backplane Serial Link
2 2 2 2
Channel BB
TSYS_CLK_BB RWCKBC
Channel BC
TSYS_CLK_BC RWCKBD RSYS_CLK_B2 TSYS_CLK_BD 2 2 2
Channel BD
REFCLKP_[A:B], REFCLKN_[A:B]: These are the differential reference clocks provided to the ORT82G5 device as described earlier. They are used as the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbps, the reference clocks will be at a frequency of 156.25 MHz. RWCK[AA:BD]: These are the low-speed receive clocks from the embedded core to the FPGA across the core-FPGA interface. These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCK_AA belongs to Channel AA, RWCK_AB belongs to channel AB and so on. With a reference clock input of 156.25 MHz, these clocks operate at 78.125 MHz. RCK78[A:B]: These are muxed outputs of RWCKA[A:D] and RWCKB[B:D] respectively. With a reference clock input of 156.25 MHz, these clocks operate at 78.125 MHz.
43
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
RSYS_CLK_[A:B][1:2] These clocks are inputs to the SERDES quad block A and B respectively from the FPGA. These are used by each channel as the read clock to read received data from the alignment FIFO within the embedded core. Clocks RSYS_CLK_A[1:2] are used by channels in the SERDES quad block A and RSYS_CLK_B[1:2] by channels in the SERDES quad block B. To guarantee that there is no overflow in the alignment FIFO, it is an absolute requirement that the write and read clocks be frequency locked within 0 ppm. Examples of how to achieve this are shown in the later section on recommended board-level clocking. TCK78[A:B]: This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the 4 transmit SERDES clocks per quad operating at up to 92.5 MHz in the embedded core. There is one clock output per SERDES quad block. TSYS_CLK[AA,...BD]: These clocks are inputs to the SERDES quad block A and B respectively from the FPGA. These are used by each channel to control the timing of the Transmit Data Path. To guarantee correct transmit operation theses clocks must be frequency locked within 0 ppm to TCK78[A:B].
Transmit and Receive Clock Rates
Table 16 shows the typical relationship between the data rates, the reference clock, the transmit TCK78[A:B] clock and the receive RCK78[A:B] clock. The selection of full-rate or half-rate for a given reference clock speed is set by bits in the transmit and receive control registers and can be set per channel. Table 16. Transmit Data and Clock Rates
TCK78[A: B] and RCK78[A:B] Clocks 15 MHz 25 MHz 31.25 MHz 50 MHz 62.5 MHz 78 MHz 92.5 MHz Rate of Channel Selected as Clock Source Half Half Half Full Full Full Full
Data Rate 0.6 Gbps 1.0 Gbps 1.25 Gbps 2.0 Gbps 2.5 Gbps 3.125 Gbps 3.7 Gbps
Reference Clock 60 MHz 100 MHz 125 MHz 100 MHz 125 MHz 156 MHz 185 MHz
Besides taking in a TSYS_CLK_xx from the FPGA logic for each channel, the transmit path logic sends back a clock of the same frequency, but arbitrary phase. This clock, TCK78[A:B], is derived from the MUX block of one of the 4 channels in its SERDES quad. The MUX blocks provide the potential source for TCK78[A:B] by a divide-by-4 of the SERDES STBC311xs clock used in synchronizing the transmit data words in the STBC311xx clock domain. The STBC311xx clocks are internal to the core and are not brought across the core/FPGA interface. The receiver section receives high-speed serial data at its differential CML input port and sends in to the Clock and Data Recovery (CDR) block. The CDR block then generates a recovered clock (RWCKxx) and retimes the data. Thus, the recovered receive clocks are asynchronous between channels.
Transmit Clock Source Selection
The TCKSEL[0:1][A:B] bits select the source channel of TCK78[A:B]. The selection of the source for TCK78[A:B] is controlled by these bits as shown in Table 17.
44
Lattice Semiconductor
Table 17. TCK78[A:B] Source Selection
TCKSEL0 0 1 0 1
ORCA ORT42G5 and ORT82G5 Data Sheet
TCKSEL1 0 0 1 1
Clock Source Channel A Channel B Channel C Channel D
Recommended Transmit Clock Distribution for the ORT82G5
As an example of the recommended clock distribution approach, TSYS_CLK_A[A:D] can be sourced by TCK78A as shown in Figure 25 if the transmit line rate are common for all four channels in a quad. Similar clocking would be used for Quad B. Figure 25. Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
TCK78A TSYS_CLK_AA
Common Logic, Quad A Channel AA
2
REFCLK[P:N]_A
156.25 MHz
FPGA Logic
TSYS_CLK_AB
Channel AB
Four Channels of 3.125 Gbps Outgoing Serial Data
TSYS_CLK_AC
Channel AC
TSYS_CLK_AD
Channel AD
All Clocks at 78.125 MHz
If the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in Figure 26 can be used. The figure shows TSYS_CLK_AA and TSYS_CLK_AB being sourced by TCK78A and TSYS_CLK_AC and TSYS_CLK_AD being sourced by TCK78A/2 (the division is done in FPGA logic). Similar clocking would be used for Quad B.
45
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 26. Mixed Rate Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
TCK78A Channel AA Selected as Clock Source TSYS_CLK_AA
50 MHz
Common Logic, Quad A Channel AA
2
REFCLK[P:N]_A
100 MHz
FPGA Logic
TSYS_CLK_AB
Channel AB
Two Channels of 2.0 Gbps (Full-Rate) Outgoing Serial Data
/2
TSYS_CLK_AC
Channel AC
TSYS_CLK_AD 25 MHz
Channel AD
Two Channels of 1.0 Gbps (Half-Rate) Outgoing Serial Data
Receive Clock Source Selection and Recommended Clock Distribution In the receive path, one clock per bank of four channels, called RCK78[A:B], is sent to the FPGA logic. The control register bits RCKSEL[0:1][A:B] are used to select the clock source for these clocks. The selection of the source for RCK78[A:B] is controlled by these bits as shown in Table 18. Table 18. RCK78[A:B] Source Selection
RCKSEL0 0 1 0 1 RCKSEL1 0 0 1 1 Clock Source Channel A Channel B Channel C Channel D
In the receive channel alignment bypass mode the data and recovered clocks for the eight channels (four per SERDES quad) are independent. The data for each channel are synchronized to the recovered clock from that channel. Figure 27. - Receive Clocking for a Single Quad (Similar Connections Would Be Used for Quad B)
78.125 MHz
RCK78A RWCKAA
Common Logic, Quad A Channel AA
2
REFCLK[P:N]_A
156.25 MHz
FPGA Logic
RSYS_CLK_A1 RWCKAB
Channel AB All Recovered Clocks at 78.125 MHZ
RWCKAC
Channel AC
Four Channels of 3.125 Gbps Incoming Serial Data
RWCKAD
Channel AD
RSYS_CLK_A2
46
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
The receive channel alignment bypass mode allows mixing of half and full line rates among the channels, as shown in Figure 28. The figure shows channel pair AA and AB configured in full rate mode at 2.0 Gbps. Channel pair AC and AD are configured in half-rate mode at 1.0 Gbps. Figure 28. Receive Clocking for Mixed Line Rates
25 MHz or 50 MHz RCK78A RWCKAA
Common Logic, Quad A Channel AA
2
REFCLK[P:N]_A
100 MHz Two Channels of 2.0 Gbps (Full-Rate) Incoming Serial Data
Recovered Clocks at 50 MHZ
FPGA Logic
Recovered Clocks at 25 MHZ
{ {
RSYS_CLK_A1 RWCKAB
Channel AB
RWCKAC
Channel AC
RWCKAD
Channel AD
RSYS_CLK_A2
Two Channels of 1.0 Gbps (Half-Rate) Incoming Serial Data
As noted in the caption of Figure 28, each quad can be configured in any line rate (0.6 to 3.7 Gbps), since each quad has its own reference clock input pins. The receive alignment FIFO per channel cannot be used in this mode.
Multi-Channel Alignment Clocking Strategies for the ORT82G5
The data on the eight channels (four per SERDES quad) in the ORT82G5 can be independent of each other or can be synchronized in several ways. For example, two channels within a SERDES can be aligned together; channel A and B and/or channel C and D. Alternatively, all four channels in a SERDES quad can be aligned together to form a communication channel with a bandwidth of 10 Gbps. Finally, the alignment can be extended across both SERDES quads to align all eight channels. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. Clocking strategies for these various modes are described in the following paragraphs. For dual alignment both twins within a quad can be sourced by clocks that are different from the other channels, however each pair of SERDES must have the same clock. The channel pair AA and AB is driven on the low speed side by RSYS_CLK_A1 and the channel pair AC and AD are driven on the low speed side by RSYS_CLK_A2. Either RWCKAA or RWCKAB can be connected to RSYS_CLK_A1 and either RWCKAC or RWCKAD can be connected to RSYS_CLK_A2. A clocking example for dual alignment is shown in Figure 29.
47
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 29. Receive Clocking for a Dual Alignment in a Single Quad (Similar Connections Would Be Used for Quad B)
RCK78A TCK78A
Common Logic, Quad A Channel AA
2
REFCLK[P:N]_A
FPGA Logic
RWCKAA RSYS_CLK_A1 TSYS_CLK_AA RWCKAB
156.25 MHz Two Bidirectional Channels of 3.125 Gbps Serial Data
Channel AB
TSYS_CLK_AB RWCKAC
Channel AC
TSYS_CLK_AC RWCKAD RSYS_CLK_A2 TSYS_CLK_AD
Channel AD
Two Bidirectional Channels of 3.125 Gbps Serial Data
All Clocks at 78.125 MHZ
For receive quad alignment, RSYS_CLK_[A1,B1] and RSYS_CLK_[A2,B2] can be tied together as shown for quad A and B in Figure 30. In receive eight-channel alignment, either RCK78A or RCK78B can be used to source RSYS_CLK_[A1,A2] and RSYS_CLK_[B1,B2] as shown in Figure 31. Figure 30. Clocking for Quad Alignment in a Single Quad (Similar Connections Would Be Used for Quad B)
RCK78A TCK78A
Common Logic, Quad A Channel AA
2
REFCLK[P:N]_A
FPGA Logic
RWCKAA RSYS_CLK_A1 TSYS_CLK_AA RWCKAB
156.25 MHz
Channel AB
TSYS_CLK_AB RWCKAC
Channel AC
TSYS_CLK_AC RWCKAD RSYS_CLK_A2 TSYS_CLK_AD
Four Bidirectional Channels of 3.125 Gbps Serial Data
Channel AD
All Clocks at 78.125 MHZ
48
Lattice Semiconductor
Figure 31. Clocking for Eight Channel Alignment
RCK78A TCK78A RWCKAA RSYS_CLK_A1 TSYS_CLK_AA RWCKAB
ORCA ORT42G5 and ORT82G5 Data Sheet
Common Logic, Quad A Channel AA
2 REFCLK[P:N]_A
156.25 MHz
Channel AB
TSYS_CLK_AB RWCKAC
Channel AC
TSYS_CLK_AC RWCKAD RSYS_CLK_A2
Channel AD
Eight Bidirectional Channels of 3.125 Gbps Serial Data
FPGA Logic
TSYS_CLK_AD RCK78B TCK78B RWCKBA RSYS_CLK_B1 TSYS_CLK_BA RWCKBB REFCLK[P:N]_B 2
Common Logic, Quad B Channel BA
Channel BB
TSYS_CLK_BB RWCKBC TSYS_CLK_BC RWCKBD RSYS_CLK_B2 TSYS_CLK_BD
Channel BC
Channel BD
All Clocks at 78.125 MHz
Reset Operation
The SERDES block can be reset in one of three different ways as follows: on power up, using the hardware reset, or via the microprocessor interface. The power up reset process begins when the power supply voltage ramps up to approximately 80% of the nominal value of 1.5V. Following this event, the device will be ready for normal operation after 3 ms. A hardware reset is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function affects all SERDES channels and resets all microprocessor and internal registers and counters. Using the software reset option, each channel can be individually reset by setting SWRST (bit 2) to a logic 1 in the channel configuration register. The device will be ready 3 ms after the SWRST bit is deasserted. Similarly, all four channels per quad SERDES can be reset by setting the global reset bit GSWRST. The device will be ready for normal operation 3 ms after the GSWRST bit is deasserted. Note that the software reset option resets only SERDES internal registers and counters. The microprocessor registers are not affected. It should also be noted that the embedded block cannot be accessed until after FPGA configuration is complete.
49
Lattice Semiconductor Start Up Sequence for the ORT42G5
ORCA ORT42G5 and ORT82G5 Data Sheet
The following sequence is required by the ORT42G5 device. For information required for simulation that may be different than this sequence, see the ORT42G5 Design Kit. 1. Initiate a hardware reset by making PASB_RESETN low. Keep this low during FPGA configuration of the device. The device will be ready for operation 3 ms after the low to high transition of PASB_RESETN. 2. At startup, the legacy SERDES channel logic must be powered down and removed from any multi-channel alignment groups: * Setting bit 1 to one in registers at locations 30002, 30012, 30102, 30112, 30003, 30013, 30103 and 30113 powers down the legacy logic. (Note that the reset value for these bits is 0.) * Setting bits 4 and 5 to zero (reset condition) in the register at locations 30810 and 30910 removes the legacy logic from any alignment group. 3. Configure the following SERDES internal and external registers. Note that after device initialization, all alarm and status bits should be read once to clear them. A subsequent read will provide the valid state. Set the following bits in register 30800: - Bits LCKREFN_[AC and AD] to 1, which implies lock to data. - Bits ENBYSYNC_[AC and AD] to 1 which enables dynamic alignment to comma. Set the following bits in register 30801: - Bits LOOPENB_[AC and AD] to 1 if high-speed serial loopback is desired. Set the following bits in register 30900: - Bits LCKREFN_[BC and BD] to 1 which implies lock to data. - Bits ENBYSYNC_[BC and BD] to 1 which enables dynamic alignment to comma. Set the following bits in register 30901: - Bits LOOPENB_[BC and BD] to 1 if high-speed serial loopback is desired. Set the following bits in registers 30022, 30032, 30122, 30132: - TXHR set to 1 if TX half-rate is desired. - 8b10bT set to 1 if 8b10b encoding is desired. Set the following bits in registers 30023, 30033, 30123, 30133: - RXHR Set to 1 if RX half-rate is desired. - 8b10bR set to 1 if 8b10b decoding is desired. - LINKSM set to 1 if the Fibre Channel state machine is desired. Assert GSWRST bit by writing 1's to both SERDES blocks. Deassert GSWRST bit by writing 0's to both SERDES blocks. Wait 3 ms. If higher speed serial loopback has been selected, the receive PLLs will use this time to lock to the new serial data. Monitor the following alarm bits in registers 30020, 30030, 30120, 30130: - LKI, PLL lock indicator. 1 indicates that PLL has achieved lock. 4. If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three times: - K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma/) in FC mode. - /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI mode.
50
Lattice Semiconductor Start Up Sequence for the ORT82G5
ORCA ORT42G5 and ORT82G5 Data Sheet
The following sequence is required by the ORT82G5 device. For information required for simulation that may be different than this sequence, see the ORT82G5 Design Kit. 1. Initiate a hardware reset by making PASB_RESETN low. Keep this low during FPGA configuration of the device. The device will be ready for operation 3 ms after the low to high transition of PASB_RESETN. 2. Configure the following SERDES internal and external registers. Note that after device initialization, all alarm and status bits should be read once to clear them. A subsequent read will provide the valid state. Set the following bits in register 30800: - Bits LCKREFN_[AA:AD] to 1, which implies lock to data. - Bits ENBYSYNC_[AA:AD] to 1 which enables dynamic alignment to comma. Set the following bits in register 30801: - Bits LOOPENB_[AA:AD] to 1 if high-speed serial loopback is desired. Set the following bits in register 30900: - Bits LCKREFN_[BA:BD] to 1 which implies lock to data. - Bits ENBYSYNC_[BA:BD] to 1 which enables dynamic alignment to comma. Set the following bits in register 30901: - Bits LOOPENB_[BA:BD] to 1 if high-speed serial loopback is desired. Set the following bits in registers 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132: - TXHR set to 1 if TX half-rate is desired. - 8B10BT set to 1 Set the following bits in registers 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133: - RXHR Set to 1 if RX half-rate is desired. - 8B10BR set to 1. - LINKSM set to 1 if the Fibre Channel state machine is desired. Assert GSWRST bit by writing two 1's. Deassert GSWRST bit by writing two 0's. Wait 3ms. If higher speed serial loopback has been selected, the receive PLLs will use this time to lock to the new serial data. Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130: - LKI, PLL lock indicator. 1 indicates that PLL has achieved lock. 3. If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three times: - K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma/) in FC mode. - /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI mode.
51
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Test Modes
In addition to the operational logic described in the preceding sections, the Embedded Core contains logic to support various test modes - both for device validation and evaluation and for operating system level tests. The following sections discuss two of the test support logic blocks, supporting various loopback modes and SERDES characterization.
Loopback Testing
Loopback testing is performed by looping back (either internal to the Embedded Core, by configuring the FPGA logic or by external connections) transmitted data to the corresponding receiver inputs, or received data to the transmitter output. The loopback path may be either serial or parallel. In general, loopback tests can be classified as "near end" or "far end." In "near end" loopback (Figure 32(a)), data is generated and checked locally, i.e. by logic on, or connection of, test equipment to the same card as the FPSC. In "far end" loopback (Figure 32(b)), the generating and checking functions are performed remotely, either by test equipment or a remote system card. Figure 32. "Near End" vs. "Far End" Loopback
Device Under Test (DUT)
Test Equipment or Logic on Local System Card
{
Data Checking
FPGA Logic m MRWDxx[39:0] 40
Receive
Embedded Core
CML Buffer CML Buffer
HDIN[P:N]_xx 2
Non-Functional
Data Generation
n
TWDxx[31:0] TCOMMAxx[3:0] TBIT9xx[3:0]
32 4 4
Transmit
HDOUT[P:N]_xx 2
Active (to Eye Diagram Measurement or remote System Card)
(a) "Near End" Loopback
High Speed Serial Loopback Connection
Device Under Test (DUT)
m
Active (to Logic on Local System Card)
MRWDxx[39:0]
40
DE MUX
2
8B/10B SERDES CML Buffer
Data Generation
Receive
HDOUT[P:N]_xx
n
Non-Functional
TWDxx[31:0] TCOMMAxx[3:0] TBIT9xx[3:0]
32 4 4
Transmit
8B/10B
SERDES
CML Buffer
2
Data Checking
(b) "Far End" Loopback
Parallel Loopback Connection
The loopback mode can also be characterized by the physical location of the loopback connection. There are three possible loopback modes supported by the Embedded Core logic: * High-speed serial loopback at the CML buffer interface (near end) * Parallel loopback at the SERDES boundary (far end)
52
{
FPGA Logic
Embedded Core
SERDES Block
HDIN[P:N]_xx
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
* Parallel loopback at MUX/DEMUX boundary excluding SERDES (near end) The three loopback modes are described in more detail in the following sections. As noted earlier, other specialized loopback modes can be obtained by configuration of the FPGA logic or by connections external to the FPSC.
High-Speed Serial Loopback at the CML Buffer Interface
The high-speed serial loopback mode has the serial transmit signals looped back internally to the serial receive circuitry. The internal loopback path is from the input connection to the transmit CML buffer to the output connection from the receive CML buffer. The data are sourced on the TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal lines and received on the MRWDxx[39:0] signal lines. The serial loopback path does not include the high-speed input and output buffers. If TESTEN_xx is set, the HDOUTP_xx and HDOUTN_xx outputs are active in this mode while the CML input buffers are powered down. The device is otherwise in its normal mode of operation. This mode is normally used for tests where the data source and destination are on the same card and is the basic loopback path shown earlier in Figure 32(a). The data rate selection bits, TXHR and RXHR, in the channel configuration registers must be configured to carry the same value. Table 19 and Table 20 summarize the settings of the control interface register configuration bits for high-speed serial loopback. Table 19. High-Speed Serial Loopback Configuration Bit Definitions for the ORT42G5
Register Address 30022, 30032, 30122, 30132 Bit Value Bit 0 = 0 or 1 Bit 7 = 0 or 1 Bit Name TXHR 8B10BT Comments Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to the same value. Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to the same value.
30023, 30033, 30123, 30133
Bit 0 = 0 or 1 Bit 3 = 0 or 1
RXHR 8B10BR
30801, 30901
Bit 2 = 1 (Channel C) LOOPENB_xx Set any of the bits 0-3 to 1 to do serial loopback on the corresponding channel.* The high speed serial outputs will not be Bit 3 = 1 (Channel D) active.
*This test mode can also be set using TESTEN_xx in place of LOOPENB_xx. In that case, Test Mode must be set to 00000.
Table 20. High-Speed Serial Loopback Configuration Bit Definitions for the ORT82G5
Register Address 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 Bit Value Bit 0 = 0 or 1 Bit 7 = 0 or 1 Bit Name TXHR 8B10BT Comments Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to the same value. Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to the same value.
30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133
Bit 0 = 0 or 1 Bit 3 = 0 or 1
RXHR 8B10BR
53
Lattice Semiconductor
Register Address 30801, 30901
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit Value
Bit Name
Comments
Bit 0 =1 (Channel A) LOOPENB_xx Set any of the bits 0-3 to 1 to do serial loopback on the corresponding channel.* The high speed serial outputs will not be Bit 1 = 1 (Channel B) active. Bit 2 = 1 (Channel C) Bit 3 = 1 (Channel D)
*This test mode can also be set using TESTEN_xx in place of LOOPENB_xx. In that case, Test Mode must be set to 00000.
Parallel Loopback at the SERDES Boundary
In this parallel loopback differential data are received at the HDINP_xx and HDINN_xx pins and are retransmitted at the HDOUTP_xx and HDOUTN_xx pins. The loopback path is at the interface between the SERDES blocks and the MUX and DEMUX blocks and uses the parallel 10-bit buses at these interfaces (see Figure 32b). The loopback connection is made such that the input signals to the TX SERDES block is the same as the output signals from the RX SERDES block. In this parallel loopback mode, the MRWDxx[39:0] signal lines remain active and the TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal lines are not used. This mode is normally used for tests where serial test data is received from and transmitted to either test equipment or via a serial backplane to a remote card and is the basic loopback path shown earlier in Figure 32(b). The data rate selection bits TXHR and RXHR in the channel configuration registers must be configured to carry the same value. Also, the 8b/10b encoder and decoder are excluded from the loopback path by setting the 8b10bT and 8b10bR configuration bits to 0. Table 21 and Table 22 illustrate the control interface register configuration for the parallel loopback. Table 21. Parallel Loopback at the SERDES Boundary Configuration Bit Definitions
Register Address (Hex) 30022, 30032, 30122, 30132 30023, 30033, 30123, 30133 30005, 30105 30026, 30036, 30126, 30136 Bit Value Bit 0 = 0 or 1 Bit 7 = 0 Bit 0 = 0 or 1 Bit 3 = 0 Bit 7 = 1 Bits[4:0] Bit Name TXHR 8b10bT RXHR 8b10bR GTESTEN Testmode Comments Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0 The 8b/10b encoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to 0. Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0.The 8b/10b decoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to 0. SET to 1 if the loopback is done globally on both channels. Set to 00001
Table 22. Parallel Loopback at the SERDES Boundary Configuration Bit Definitions for the ORT82G5
Register Address (Hex) 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 30005, 30105 30006, 30016, 30026, 30036, 30106, 30116, 30126, 30136 Bit Value Bit 0 = 0 or 1 Bit 7 = 0 Bit 0 = 0 or 1 Bit 3 = 0 Bit 7 = 1 Bits[4:0] Bit Name TXHR 8b10bT RXHR 8b10bR GTESTEN Testmode Comments Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0 The 8b/10b encoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to 0. Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0.The 8b/10b decoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to 0. SET to 1 if the loopback is done globally on all four channels. Set to 00001
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Parallel Loopback at MUX/DEMUX Boundary, Excluding SERDES
This is a low-frequency test mode used to test the MUX/DEMUX logic block. As with the mode described in the previous section, the loopback path is at the interface between the SERDES blocks and the MUX and DEMUX blocks and uses the parallel 10-bit buses at these interfaces (see Figure 33). However, the loopback connection is made such that the output signals from the TX MUX block are used as the input signals to the RX SERDES block. In this loopback mode the MRWDxx[39:0], TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal lines function normally and the high-speed serial input and output buffers are not used. Use of this mode also requires configuration of the FPGA logic to connect the MRWDxx[39:0], TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal lines to external pins. The basic loopback path is shown in Figure 33. Figure 33. Parallel Loopback at MUX/DEMUX Boundary, Excluding SERDES
Test Equipment
{
Data Checking
FPGA Logic m MRWDxx[39:0] 40
Receive
Embedded Core
DEMUX
Data Generation
n
TWDxx[31:0] TCOMMAxx[3:0] TBIT9xx[3:0]
32 4 4
Transmit
MUX
Parallel Loopback Connection
This test mode is enabled by setting the pin PLOOP_TEST_ENN to 0. PASB_TESTCLK must be running in this mode at 4x frequency of RSYS_CLK[A2, B2] or TSYS_CLK_[AC, AD, BC, BD] for the ORT42G5 and RSYS_CLK[A1,A2,B1,B2] or TSYS_CLK_[AA, AB... BD] for the ORT82G5.
SERDES Characterization Test Mode (ORT82G5 Only)
The SERDES characterization mode is a test mode that allows for direct control and observation of the transmit and receive SERDES interfaces at chip ports. With these modes the SERDES logic and I/O can be tested one channel at a time in either the receive or transmit modes. The SERDES characterization mode is available for only one quad (quad B) of the ORT82G5. The characterization test mode is configured by setting bits in the control registers via the system bus. There are four bits that set up the test mode. The transmit characterization test mode is entered when SCHAR_ENA=1 and SCHAR_TXSEL=1. Entering this mode will cause chip port inputs to directly control the SERDES low-speed transmit ports of one of the channels as shown in Table 23. Table 23. SERDES Transmit Characterization Mode
Chip Port PSCHAR_CKIO0 PSCHAR_LDIO[9:0] SERDES Input TBCBx LDINBx[9:0]
The x in the table will be a single channel in SERDES quad B, selected by the SCHAR_CHAN control bits. The decoding of SCHAR_CHAN is shown in Table 24.
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Lattice Semiconductor
Table 24. Decoding of SCHAR_CHAN
SCHAR_CHAN0 0 1 0 1
ORCA ORT42G5 and ORT82G5 Data Sheet
SCHAR_CHAN1 0 0 1 1
Channel BA BB BC BD
The receive characterization test mode is entered when SCHAR_ENA=1 and SCHAR_TXSEL=0, In this mode, one of the channels of SERDES outputs is observed at chip ports as shown in Table 25. The channel that is observed is also based on the decoding of SCHAR_CHAN as shown in Table 25. Table 25. SERDES Receive Characterization Mode
SERDES Output BYTSYNCBx WDSYNCBx CVOBx LDOUTBx[9:0] RBC0Bx RBC1Bx Chip Port PSCHAR_BYTSYNC PSCHAR_WDSYNC PSCHAR_CV PSCHAR_LDIO[9:0] PSCHAR_CKIO0 PSCHAR_CKIO1
Embedded Core Block RAM
There are two independent memory blocks (labeled A and B) built-into the Embedded ASIC Core (EAC). Each memory block has a capacity of 4K words by 36 bits. These two memory blocks (also called "slices") are in addition to the block RAMs found in the FPGA portion of the ORT82G5. Although the memory blocks/slices are in the EAC part of the chip, they do not interact with the rest of the EAC circuits, but are standalone memories designed specifically to increase RAM capacity in the ORT82G5 chip. They can be used by logic implemented in the FPGA portion of the FPSC. Figure 34 represents one of the two available memory slices built into the EAC. The index "x" refers to the memory slice (x=A for slice A, x=B for slice B). Each memory slice is organized into two sections, which are also labeled as A and B. In Figure 34, SDRAM A is one section of slice x, and SDRAM B is another section of slice x. Data can be written to both sections of a slice independently. However, a read access can access only one of sections A or B at any given time (CSR_x=0 selects section A, CSR_x=1 selects section B). The 36 bits written to or read from the memory slice are composed of 32 bits of data (bits 31:24, 23:16, 15:8, 7:0), and 4 bits of parity (bits 35,34,33,32). The core performs no parity checking functions. The data read from the memory is registered so that it works as a pipelined synchronous memory block. For illustration purposes, assuming that the memory slice in Figure 34 is slice A (x=A), then certain signals apply to both sections of slice A. These include D_A[35:0], CKW_A, AW_A[10:0], BYTEWN_A[3:0], Q_A[35:0], CKR_A, CSR_A, and AR_A[10:0]. The BYTEWN_A[3:0] are byte and parity write enable bits for each byte and parity bit of data being written. BYTEWN_A[3] is associated with D_A[35,31:24]. BYTEWN_A[2] is associated with D_A[34,23:16]. BYTEWN_A[1] is associated with D_A[33,15:8]. BYTEWN_A[0] is associated with D_A[32,7:0]. The signals that are unique to each section of slice A are: CSWA_A --enables writing to section A of slice A CSWB_A -- enables writing to section B of slice A 56
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
As mentioned earlier, both sections of a slice can be written independently / simultaneously, due to the independent CSW per section. The same signal illustration above applies to slice B by changing _A to _B. SDRAM A and SDRAM B in Figure 34 refer to the built-in sections A and B of one EAC RAM slice. These SDRAMS should not be confused with the FPGA SDRAMS, which are generated through Module Generator in ispLEVER. The EAC SDRAMs are always built-in to the embedded core section of the ORT82G5/42G5 and their pins are accessed through the EAC interface. In order for these pins to be available at the interface in the generated HDL models from ispLEVER, the "Use the Extra Memory in FPSC Core" checkbox needs to be checked in the customization window (after hitting the "customize" button) in Module Generator, while generating the ORT82G5/42G5 core HDL. These signals will not otherwise show in the interface model. Figure 35 and Figure 36 show, per slice, timing diagrams for both write and read accesses. These figures do not include the _x section, which refers to either slice A or B, even though this is implied. Signal names and functions are summarized in Table 26 and follow the general ORCA Series 4 naming conventions. Figure 34. Block Diagram, Embedded Core Memory Slice
FPGA Logic
Note: x=[A,B] Slice Identifier D_x[35:0] CKW_x 36
2K x 36 Memory (SRAM A)
2K x 36 Memory (SRAM B)
Side A / Side B Write Selects
CSWA_x CSWB_x AW_x[10:0] BYTEWN_x[3] BYTEWN_x[2] BYTEWN_x[1] BYTEWN_x[0] 11
Write Ports
Data
Parity
BW[35,31:24] BW[34,23:16] BW[33,15:8] BW[32,7:0]
Q_x[35:0]
36
4K x 36 Memory Slice (1 of 2)
RAM Block Read Selects
CKR_x CSR_x AR_x[10:0] 11
Read Ports
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Figure 35. Minimum Timing Specs for Memory Blocks-Write Cycle (-1 Speed Grade)
1.5 ns CKW 0.5 ns CSW[A,B] 0.3 ns 2.0 ns
0.5 ns AW[10:0] 0.5 ns D[35:0] 0.7 ns BYTEWN[3:0]
0.3 ns
0.3 ns
0.3 ns
Figure 36. Minimum Timing Specs for Memory Blocks-Read Cycle (-1 Speed Grade)
1.5 ns CKR 4.5 ns AR[10:0], CSR 0.5 ns Q[35:0] 2.0 ns 0 ns 1.5 ns
In Table 26, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out of the embedded core.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 26. Embedded Memory Slice Core/FPGA Interface Signal Description
FPGA/Embedded Core Interface Signal Name] Memory Slice Interface Signals D_[A:B][35:0] CKW_[A:B] CSWA_[A:B] CSWB_[A:B] AW_[A:B][10:0] BYTEWN_[A:B][3:0] Q_[A:B][35:0] CKR_[A:B] CSR_[A:B] AR_[A:B][10:0] I I I I I I O I I I Data in--memory slice [A:B] Write clock--memory slice [A:B]. Write chip select for SRAM A--memory slice [A:B]. Write chip select for SRAM B--memory slice [A:B]. Write address--memory slice [A:B]. Write control pins for byte-at-a-time write-memory slice [A:B]. Data out--memory slice [A:B]. Read clock--memory slice [A:B]. Read chip select--memory slice [A:B]. CSR_[A:B]= 0 selects SRAM A. CSR_[A:B]= 1 selects SRAM B. Read address--memory slice [A:B]. Input (I) to or Output (O) from Core
Signal Description
Memory Maps
Definition of Register Types
The SERDES blocks within the ORT42G5 and ORT82G5 cores have a set of status and control registers for SERDES operation. There is also other group of status and control registers which are implemented outside the SERDES, which are related to the SERDES and other functional blocks in the FPSC core. (Addresses for the control and status registers for the FPGA portion of the device are detailed in the ORCA Series 4 FPGAs data sheet, which also describes the functions of those registers).
ORT42G5 Memory Map
Each ORT42G5 SERDES block has two independent channels. Each channel is identified by both a quad identifier, A or B, and a channel identifier, C or D. (This naming convention follows that of the ORT82G5.) The registers in ORT42G5 are 8-bit memory locations, which can be classified into Status Register and Control Register. Status Register Read-only register to convey the status information of various operations within the FPSC core. An example is the state of the XAUI link-state-machine. Control Register Read-write register to set up the control inputs that define the operation of the FPSC core. Reserved addresses for the FPSC register blocks are shown in Table 29. Table 27. Structural Register Elements
Address (0x) 300xx 301xx 308xx 309xx 30A0x SERDES A, internal registers. SERDES B, internal registers. Channel A [C or D] registers (external to SERDES blocks). Channel B [C or D] registers (external to SERDES blocks). Global registers (external to SERDES blocks). Description
Table 28 details the memory map for the FPSC portion of the ORT42G5 device. In both Table 29 and Table 28, the addresses are given as 18-bit hexadecimal (18'h) values. The address may be sourced either through the MicroProcessor Interface or a User Master Interface. The MicroProcessor Interface (MPI) address bus is a 32-bit bus 59
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
which follows the Power PC convention where address bit 0 is the MSb and address bit 31 is the LSb. The MPI maps bits MPI_ADDR[14:31] to bits [17:0] of the system address bus. The User Master Interface (UMI) has an 18bit address bus and uses the opposite notation, where address line 17 is the MSb and address line 0 is the LSb. The UMI maps bits um_addr[17:0] to bits [17:0] of the system address bus. Because of the address mapping done by the MPI and UMI, the same hexadecimal address value is valid for both interfaces. The UMI, internal and microprocessor interface data buses have both 32-bit data and 4-bit parity fields and the data fields are mapped 1:1 to each other, i.e., bit 0 is bit 0 for all three buses. The bit ordering is specific to the targeted functional block. In the memory map, only bits [0:7] are specified and the convention followed for sub-field descriptions is to map the bits in the description directly to the bit order given in the bit column. For example, to select channel C as the source for the transmit and receive clocks, the register at location 30A00 should have bits 0, 2, 4 and 6 set to zero and bits 1, 3, 5 and 7 set to one. In the example in the previous paragraph, the bits being set are control bits and are independent of the MSb/LSb convention used. The resulting bit pattern 01010101 maps to the hexadecimal value AA if the left-most bit is considered the LSb and to 55 if the right-most bit is considered the LSb. In some cases, however, the data represents the value of a specific parameter, such as a size or threshold level, and the value may be stored at more than one address location, since each location can hold only 8 bits of data. For a given register, either the MSb or the LSb bit position is specified explicitly in the memory map. If the parameter value extends over multiple register locations, the relative bit or byte ordering is also specified. For additional information on the MPI and the system bus, see Technical Note TN1017, ORCA Series 4 MPI/System Bus. Table 28. ORT42G5 Memory Map
(0x) Absolute Address 30020 - AC 30030 - AD 30120 - BC 30130 - BD Reset Value (0x) 00 Reserved Receive PLL Lock Indication, Channel xx. LKI_xx = 1 indicates the receive PLL is locked. Reserved Reserved Not used FF Reserved, must be set to 1. Set to 1 on device reset. Mask Receive PLL Lock Indication, Channel xx. Reserved. Must be set to 1. Set to 1 on device reset. Reserved. Must be set to 1. Set to 1 on device reset. Reserved. Must be set to 1. Set to 1 on device reset. Reserved. Must be set to 1. Set to 1 on device reset. Reserved. Must be set to 1. Set to 1 on device reset. Reserved. Must be set to 1. Set to 1 on device reset.
Bit [0] [1] [2] [3]
Name Reserved LKI_xx Not used Not used
Description
SERDES Alarm Registers (Read Only, Clear on Read), xx = [AC, AD, BC or BD]
[4:7] Not used 30021 - AC 30031 - AD 30121 - BC 30131 - BD [0] [1] [2] [3] [4] [5] [6] [7] Reserved MLKI_xx Reserved Reserved Reserved Reserved Reserved Reserved
SERDES Alarm Mask Registers (Read/Write), xx = [AC, AD, BC or BD]
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Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
(0x) Absolute Address 30022 - AC 30032 - AD 30122 - BC 30132 - BD [1] PWRDNT_xx Reset Value (0x) 00
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0]
Name TXHR_xx
Description Transmit Half Rate Selection Bit, Channel xx. When TXHR_xx = 1, HDOUT_xx's baud rate = (REFCLK[A:B]*10) and TCK78[A:B] =(REFCLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's baud rate = (REFCLK[A:B]*20) and TCK78[A:B]=(REFCLK[A:B]/2). TXHR_xx = 0 on device reset. Transmit Powerdown Control Bit, Channel xx. When PWRDNT_xx = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT_xx = 0 on device reset. Transmit Preemphasis Selection Bit 0, Channel xx. PE0_xx and PE1_xx select one of three preemphasis settings for the transmit section. PEO_xx=PE1_xx = 0, Preemphasis is 0% PEO_xx=1, PE1_xx = 0 or PEO_xx=0, PE1_xx = 1, Preemphasis is 12.5% PEO_xx=PE1_xx = 1, Preemphasis is 25%. PEO_xx=PE1_xx = 0 on device reset. Transmit Half Amplitude Selection Bit, Channel xx. When HAMP_xx = 1, the transmit output buffer voltage swing is limited to half its normal amplitude. Otherwise, the transmit output buffer maintains its full voltage swing. HAMP_xx = 0 on device reset. Reserved. Must be set to 0. Set to 0 on device reset. Reserved Transmit 8b/10b Encoder Enable Bit, Channel xx. When 8b10bT_xx = 1, the 8b/10b encoder in the transmit path is enabled. Otherwise, the data is passed unencoded. 8b10bT_xx = 0 on device reset.
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), xx = [AC, AD, BC or BD]
[2] [3]
PE0_xx PE1_xx
[4]
HAMP_xx
[5] [6] [7]
Reserved Reserved 8b10bT_xx
30023 - AC 30033 - AD 30123 - BC 30133 - BD
[0]
RXHR_xx
20
Receive Half Rate Selection Bit, Channel xx. When RXHR_xx =1, HDIN_xx's baud rate = (REFCLK[A:B]*10) and RCK78[A:B]=(REFCLK[A:B]/4); when RXHR_xx=0, HDIN_xx's baud rate = (REFCLK[A:B]*20) and RCK78[A:B]=(REFCLK/2). RXHR_xx = 0 on device reset. Receiver Power Down Control Bit, Channel xx. When PWRDNR_xx = 1, sections of the receive hardware are powered down to conserve power. PWRDNR_xx = 0 on device reset. Reserved. Set to 1 on device reset. Receive 8b/10b Decoder Enable Bit, Channel xx. When 8b10bR = 1, the 8b/10b decoder in the receive path is enabled. Otherwise, the data is passed undecoded. 8b10bR_xx = 0 on device reset. Link State Machine Enable Bit, Channel xx. When LINKSM_xx = 1, the receiver Fiber Channel link state machine is enabled. Otherwise, the Fibre Channel link state machine is disabled. Note: LINKSM_xx is ignored when XAUI_MODE_xx=1. LINKSM_xx = 0 on device reset. Not used.
[1]
PWRDNR_xx
[2] [3]
Reserved 8b10bR_xx
[4]
LINKSM_xx
[5:7] Not used
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Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
(0x) Absolute Address 30024 - AC 30034 - AD 30124 - BC 30134 - BD [2] SWRST_xx Reset Value (0x)
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0] [1]
Name Reserved MASK_xx
Description
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), xx = [AC, AD, BC or BD] See Reserved, must be 0. Set to 0 on device reset. Bit Transmit and Receive Alarm Mask Bit, Channel xx. When MASK_xx = 1, Desc. the transmit and receive alarms of a channel are prevented from generating an interrupt (i.e., they are masked or disabled). The MASK_xx bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK_xx = 1 on device reset. Transmit and Receive Software Reset Bit, Channel xx. When SWRST_ss = 1, this bit provides the same function as the hardware reset, except that all configuration register settings are unaltered. This is not a self-clearing bit. Once set, this bit must be manually set and cleared. SWRST = 0 on device reset. Not used Transmit and Receive Test Enable Bit, Channel xx. When TESTEN_xx = 1, the transmit and receive sections are placed in test mode. The TestMode_[A:B][4:0] bits in the Global Control Registers specify the particular test, and must also be set. Note: When the global test enable bit GTESTEN_[A:B] = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN_[A:B] = 1, all channels in a block are set to test mode regardless of their TESTEN setting. TESTEN_xx = 0 on device reset. See Reserved, must be 0. Set to 0 on device reset. Bit Global Mask. When GMASK_[A:B] = 1, the transmit and receive alarms Desc. of both channels in the SERDES block are prevented from generating an interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit overrides the individual MASK_xx bits. GMASK_[A:B] = 1 on device reset. Software reset bit. The GSWRST_[A:B] bit provides the same function as the hardware reset for the transmit and receive sections of both channels, except that the device configuration settings are not affected when GSWRST_[A:B] is asserted. This is not a self-clearing bit. Once set, this bit must be manually set and cleared. The GSWRST_[A:B] bit overrides the individual SWRST_xx bits. GSWRST_[A:B] = 0 on device reset. Powerdown Transmit Function. When GPWRDNT_[A:B] = 1, sections of the transmit hardware for both channels are powered down to conserve power. The GPWRDNT_[A:B] bit overrides the individual PWRDNT_xx bits. GPWRDNT_[A:B] = 0 on device reset. Powerdown Receive Function. When GPWRDNR_[A:B] = 1, sections of the receive hardware for both channels are powered down to conserve power. The GPWRDNR_[A:B] bit overrides the individual PWRDNR_xx bits. GPWRDNR_[A:B] = 0 on device reset. Reserved, 1 on device reset. Not used Test Enable Control. When GTESTEN_[A:B] = 1, the transmit and receive sections of both channels are placed in test mode. The GTESTEN_[A:B] bit overrides the individual TESTEN_xx bits. GTESTEN_[A:B] = 0 on device reset. 00 Test Mode - See Test Mode section for settings Not used Reserved
[3:6] Not used [7] TESTEN_xx
SERDES Global Control Registers (Read Write) - Act on Both Channels in SERDES Block A or SERDES Block B. 30005 - A 30105 - B [0] [1] Reserved GMASK_[A:B]
[2]
GSWRST_[A:B]
[3]
GPWRDNT_[A:B]
[4]
GPWRDNR_[A:B]
[5] [6] [7]
Reserved Not used GTESTEN_[A:B]
30006 - A 30106 - B
[0:4] TestMode[A:B] [5] Not used [6:7] Reserved
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Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
(0x) Absolute Address 30800 - Ax 30900 - Bx Reset Value (0x) 00
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0] [1] [2] [3]
Name -- -- ENBYSYNC_xC ENBYSYNC_xD
Description Reserved for future use Reserved for future use ENBYSYNC_xC= 1 Enables Receiver Byte Synchronization for Channel xC. ENBYSYNC_xC = 0 on device reset. ENBYSYNC_xD = 1 Enables Receiver Byte Synchronization for Channel xA. ENBYSYNC_xD = 0 on device reset. Reserved for future use Reserved for future use LCKREFN_xC = 0 Locks the receiver PLL to reference clock for Channel xC. LCKREFN_xC =1 = Locks the receiver to data for Channel xx. NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0. LCKREFN_xC = 0 on device reset. LCKREFN_xD = 0 Locks the receiver PLL to reference clock for Channel xD. LCKREFN_xD =1 = Locks the receiver to data for Channel xA. NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0. LCKREFN_xD = 0 on device reset.
Control Registers (Read/Write), xx=[AC, AD, BC or BD]
[4] [5] [6]
-- -- LCKREFN_xC
[7]
LCKREFN_xD
30801 - Ax 30901 - Bx
[0] [1] [2]
-- -- LOOPENB_xC
00
Reserved for future use Reserved for future use Enable Loopback Mode for Channel xC. When LOOPEN_xC=1, the transmitter high-speed output is looped back to the receiver high-speed input. This mode is similar to high-speed loopback mode enabled by TESTMODE_xx except that LOOPEN_xx disables the high-speed serial output. LOOPEN_xC=0 on device reset. Enable Loopback Mode for Channel xD. When LOOPEN_xD=1, the transmitter high-speed output is looped back to the receiver high-speed input. This mode is similar to high-speed loopback mode enabled by TESTMODE_xx except that LOOPEN_xx disables the high-speed serial output. LOOPEN_xD=0 on device reset. Reserved for future use Reserved for future use Word Align Disable Bit. When NOWDALIGN_xC=1, receiver word alignment is disabled for Channel xC. NOWDALIGN_xC=0 on device reset. Word Align Disable Bit. When NOWDALIGN_xD=1, receiver word alignment is disabled for Channel xD. NOWDALIGN_xD=0 on device reset.
[3]
LOOPENB_xD
[4] [5] [6] [7]
-- -- NOWDALIGN_xC NOWDALIGN_xD
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Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
(0x) Absolute Address 30810 - Ax 30910 - Bx Reset Value (0x) 00
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0]] [1] [2]
Name -- -- DOWDALIGN_xC
Description Reserved for future use Reserved for future use Word Realign Bit. When DOWDALIGN_xC transitions from 0 to 1, the receiver realigns on the next comma character for Channel xC. NOWDALIGN_xC=0 on device reset. Word Realign Bit. When DOWDALIGN_xC transitions from 0 to 1, the receiver realigns on the next comma character for Channel xC. NOWDALIGN_xC=0 on device reset. Reserved for future use. Set to zero. Reserved for future use. Set to zero. Enable multi-channel alignment for Channel xC. When FMPU_STR_EN _xC = 0, Channel xC is not part of a multi-channel alignment group When FMPU_STR_EN _xC = 1, Channel xC is part of a twin channel alignment (SERDES block A or B) or quad channel alignment (both SERDES blocks) group. Enable multi-channel alignment for Channel xD. When FMPU_STR_EN _xD = 0, Channel xD is not part of a multi-channel alignment group When FMPU_STR_EN _xD = 1, Channel xD is part of a twin channel alignment (SERDES block A or B) or quad channel alignment (both SERDES blocks) group.
[3]
DOWDALIGN_xC
[4] [5] [6]
-- -- FMPU_STR_EN _xC
[7]
FMPU_STR_EN _xD
30811 - Ax 30911 - Bx
[0:7] FMPU_SYNMODE_ [A:B]
00
Sync mode for block [A:B] 00000000 = No channel alignment 00001010 = Twin channel alignment, SERDES block [A:B] 00001111 = Quad channel alignment (both SERDES blocks) Reserved for future use. Reserved for future use. Resync a Single Channel. When FMPU_RESYNC1_xC transitions from 0 to 1, the corresponding channel xC is resynchronized (the write and read pointers are reset). FMPU_STR_EN_xC=0 on device reset. Resync a Single Channel. When FMPU_RESYNC1_xD transitions from 0 to 1, the corresponding channel xD is resynchronized (the write and read pointers are reset). FMPU_STR_EN_xD=0 on device reset. Reserved for future use. Resync a Twin-Channel Group. When FMPU_RESYNC2[A:B] transitions from a 0 to a 1, the corresponding twin-channel group is resynchronized. FMPU_RESYNC2[A:B]=0 on device reset. Reserved for future use. Controls use of XAUI link state machine in place of Fibre-Channel state machine. When XAUI_MODE[A:B]=1, both channels in the SERDES block enable their XAUI link state machines. (LINKSM_xx bits are ignored). XAUI_MODE[A:B]=0 on device reset.
30820 - Ax 30920 - Bx
[0] [1] [2]
-- -- FMPU_RESYNC1_xC
00
[3]
FMPU_RESYNC1_xD
[4] [5]
-- FMPU_RESYNC2[A:B]
[6] [7]
-- XAUI_MODE[A:B]
30821 - A 30921 - B
[0]
NOCHALGN [A:B]
00
Bypass channel alignment. NOCHALGN [A:B] =1 causes bypassing of multi-channel alignment FIFOs for the corresponding SERDES quad. NOCHALGN [A:B] =0 on device reset. Reserved for future use.
[1:7]
--
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Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
(0x) Absolute Address 30933 Reset Value (0x) 00
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0:3] [4:5] [6] [7]
Name -- -- -- -- -- --
Description Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use.
Status Registers (Read Only, Clear on Read), xx = [AC, AD, BC or BD] 30804 - Ax 30904 - Bx [0:1] [2:3] 00 Reserved for future use. Reserved for future use. XAUI Status Register. Status of XAUI link state machine for Channel xC 00 - No synchronization, 10 - Synchronization done, 11 - Not used, 01 - no_comma (see XAUI state machine) and at least one CV detected. XAUISTAT_xC[0:1] = 00 on device reset. XAUI Status Register. Status of XAUI link state machine for Channel xD 00 - No synchronization, 10 - Synchronization done, 11 - Not used, 01 - no_comma (see XAUI state machine) and at least one CV detected. XAUISTAT_xD[0:1] = 00 on device reset. 00 Reserved for future use. Reserved for future use. Status of Word Alignment. When DEMUX_WAS_xC=1, word alignment is achieved for Channel xC. DEMUX_WAS_xC=0 on device reset. Status of Word Alignment. When DEMUX_WAS_xD=1, word alignment is achieved for Channel xD. DEMUX_WAS_xD=0 on device reset. Reserved for future use. Reserved for future use. Status of Channel Alignment. When CH24_SYNC_xC=1, multi-channel alignment is achieved for Channel xC. CH24_SYNC_xC=0 on device reset. Status of Channel Alignment. When CH24_SYNC_xD=1, multi-channel alignment is achieved for Channel xD. CH24_SYNC_xD=0 on device reset. 00 Reserved for future use. Multi-Channel Overflow Status. When SYNC2_[A:B]_OVFL=1, twin channel synchronization FIFO overflow has occurred. SYNC2_[A:B]_OVFL=0 on device reset. Reserved for future use. Multi-Channel Out-Of-Sync Status. When SYNC2_[A:B]_OOS=1, twin channel synchronization has failed.
[4:5] XAUISTAT_xC
[6:7] XAUISTAT_xD
30805 - Ax 30905 - Bx
[0]] [1] [2] [3] [4] [5] [6]
-- -- DEMUXWAS_xC DEMUXWAS_xD -- -- CH24_SYNC_xC
[7]
CH24_SYNC_xD
30814 - A 30914 - B
[0] [1]
-- SYNC2_[A:B]_OVFL
[2:3] [4]
-- SYNC2_[A:B]_OOS
SYNC2_[A:B]_OOS=0 on device reset.
[5:7] -- Reserved for future use.
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Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
(0x) Absolute Address 30A00 Reset Value (0x) 00
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit
Name
Description Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES quad A 01 = Channel AC 11 = Channel AD Receive Clock Select. Controls source of 78 MHz RCK78 for SERDES quad A 01 = Channel AC 11 = Channel AD Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES quad B 01 = Channel BC 11 = Channel BD Receive Clock Select. Controls source of 78 MHz RCK78 for SERDES quad B 01 = Channel BC 11 = Channel BD
Common Control Registers (Read/Write) [0:1] TCKSELA
[2:3] RCKSELA
[4:5] TCKSELB
[6:7] RCKSELB
30A01
[0:4]
--
00
Reserved for future use LSb's for the threshold for low address in RX_FIFOs. RX_FIFO_MIN, Bit 5 is LSb.*
[5:7] RX_FIFO_MIN 30A02 [0:1] RX_FIFO_MIN [2] FMPU_RESYNC4 00
MSb's for the threshold for low address in RX_FIFOs. RX_FIFO_MIN, Bit 1 is MSb.* Resynchronize a four-channel group. When FPMPU_RESYNC4 transitions from 0 to 1, the entire four-channel group is resynchronized. FMPU_RESYNC4 = 0 on device reset Reserved for future use
[3:7] Common Status Registers 30A03 [0]
-- SYNC4_OVFL 00
Read-Only Multi-Channel Overflow Status. When SYNC4_OVFL=1, 4channel synchronization FIFO overflow has occurred. SYNC4_OVFL=0 on device reset. Read-Only Multi-Channel Out-Of-Sync Status. When SYNC4_OOS=1, 4-channel synchronization has failed. SYNC4_OOS=0 on device reset. Reserved for future use.
[1] [2:7]
SYNC4_OOS --
* Useful values for RX_FIFO_MIN [0:4] are 0 to 17(decimal)
66
Lattice Semiconductor ORT82G5 Memory Map
ORCA ORT42G5 and ORT82G5 Data Sheet
Each ORT82G5 SERDES block has eight independent channels. Each channel is identified by both a quad identifier, A or B, and a channel identifier, A, B, C or D. The registers in ORT82G5 are 8-bit memory locations, which can be classified into Status Register and Control Register. Status Register Read-only register to convey the status information of various operations within the FPSC core. An example is the state of the XAUI link-state-machine. Control Register Read-write register to set up the control inputs that define the operation of the FPSC core. Reserved addresses for the FPSC register blocks are shown in Table 29. Table 29. Structural Register Elements
Address (0x) 300xx 301xx 308xx 309xx 30A0x SERDES A, internal registers. SERDES B, internal registers. Channel A [A:D] registers (external to SERDES blocks). Channel B [A:D] registers (external to SERDES blocks). Global registers (external to SERDES blocks). Description
Table 30 details the memory map for the FPSC portion of the ORT82G5 device. In both Table 29 and Table 30, the addresses are given as 18-bit hexadecimal (18'h) values. The address may be sourced either through the Microprocessor interface or a User Master Interface. The MicroProcessor Interface (MPI) address bus is a 32-bit bus which follows the Power PC convention where address bit 0 is the MSb and address bit 31 is the LSb. The MPI maps bits MPI_ADDR[14:31] to bits [17:0] of the system address bus. The User Master Interface (UMI) has an 18bit address bus and uses the opposite notation, where address line 17 is the MSb and address line 0 is the LSb. The UMI maps bits um_addr[17:0] to bits [17:0] of the system address bus. Because of the address mapping done by the MPI and UMI, the same hexadecimal address value is valid for both interfaces. The UMI, internal and microprocessor interface data buses have both 32-bit data and 4-bit parity fields and the data fields are mapped 1:1 to each other, i.e., bit 0 is bit 0 for all three buses. The bit ordering is specific to the targeted functional block. In the memory map, only bits [0:7] are specified and the convention followed for sub-field descriptions is to map the bits in the description directly to the bit order given in the bit column. For example, to select channel C as the source for the transmit and receive clocks, the register at location 30A00 should have bits 0, 2, 4 and 6 set to zero and bits 1, 3, 5 and 7 set to one. In the example in the previous paragraph, the bits being set are control bits and are independent of the MSb/LSb convention used. The resulting bit pattern 01010101 maps to the hexadecimal value AA if the left-most bit is considered the LSb and to 55 if the right-most bit is considered the LSb. In some cases, however, the data represents the value of a specific parameter, such as a size or threshold level, and the value may be stored at more than one address location, since each location can hold only 8 bits of data. For a given register, either the MSb or the LSb bit position is specified explicitly in the memory map. If the parameter value extends over multiple register locations, the relative bit or byte ordering is also specified. For additional information on the MPI and the system bus, see Technical Note TN1017, ORCA Series 4 MPI/System Bus.
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Lattice Semiconductor
Table 30. ORT82G5 Memory Map
(0x) Absolute Address 30000 - AA 30010 - AB 30020 - AC 30030 - AD 30100 - BA 30110 - BB 30120 - BC 30130 - BD 30001 - AA 30011 - AB 30021 - AC 30031 - AD 30101 - BA 30111 - BB 30121 - BC 30131 - BD Reset Value (0x) 00 Reserved
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0] [1] [2] [3] [4:7]
Name Reserved LKI_xx Reserved Reserved Not used
Description
SERDES Alarm Registers (Read Only), xx=[AA,...,BD] Receive PLL Lock Indication, Channel xx. LKI_xx = 1 indicates the receive PLL is locked. Reserved Reserved Not used
SERDES Alarm Mask Registers (Read/Write), xx=[AA,...,BD] [0] [1] [2] [3] [4] [5] [6] [7] 30002 - AA 30012 - AB 30022 - AC 30032 - AD 30102 - BA 30112 - BB 30122 - BC 30132 - BD [0] Reserved MLKI_xx Reserved Reserved Reserved Reserved Reserved Reserved TXHR_xx 00 FF Reserved, must be set to 1. Set to 1 on device reset. Mask Receive PLL Lock Indication, Channel xx. Reserved, must be set to 1. Set to 1 on device reset. Reserved, must be set to 1. Set to 1 on device reset. Reserved, must be set to 1. Set to 1 on device reset. Reserved, must be set to 1. Set to 1 on device reset. Reserved, must be set to 1. Set to 1 on device reset. Reserved, must be set to 1. Set to 1 on device reset. Transmit Half Rate Selection Bit, Channel xx. When TXHR_xx = 1, HDOUT_xx's baud rate = (REFCLK[A:B]*10) and TCK78[A:B] =(REFCLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's baud rate = (REFCLK[A:B]*20) and TCK78[A:B]=(REFCLK[A:B]/2). TXHR_xx = 0 on device reset. Transmit Powerdown Control Bit, Channel xx. When PWRDNT_xx = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT_xx = 0 on device reset. Transmit Preemphasis Selection Bit 0, Channel xx. PE0_xx and PE1_xx select one of three preemphasis settings for the transmit section. PEO_xx=PE1_xx = 0, Preemphasis is 0% PEO_xx=1, PE1_xx = 0 or PEO_xx=0, PE1_xx = 1, Preemphasis is 12.5% PEO_xx=PE1_xx = 1, Preemphasis is 25%. PEO_xx=PE1_xx = 0 on device reset. Transmit Half Amplitude Selection Bit, Channel xx. When HAMP_xx = 1, the transmit output buffer voltage swing is limited to half its normal amplitude. Otherwise, the transmit output buffer maintains its full voltage swing. HAMP_xx = 0 on device reset. Reserved. Must be set to 0. Set to 0 on device reset. Reserved Transmit 8b/10b Encoder Enable Bit, Channel xx. When 8b10bT_xx = 1, the 8b/10b encoder in the transmit path is enabled. Otherwise, the data is passed unencoded. 8b10bT_xx = 0 on device reset.
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), xx=[AA,...,BD]
[1]
PWRDNT_xx
[2] [3]
PE0_xx PE1_xx
[4]
HAMP_xx
[5] [6] [7]
Reserved Reserved 8b10bT_xx
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Lattice Semiconductor
Table 30. ORT82G5 Memory Map (Continued)
(0x) Absolute Address 30003 - AA 30013 - AB 30023 - AC 30033 - AD 30103 - BA 30113 - BB 30123 - BC 30133 - BD Reset Value (0x) 20
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0]
Name RXHR_xx
Description Receive Half Rate Selection Bit, Channel xx. When RXHR_xx =1, HDIN_xx's baud rate = (REFCLK[A:B]*10) and RCK78[A:B]=(REFCLK[A:B]/4); when RXHR_xx=0, HDIN_xx's baud rate = (REFCLK[A:B]*20) and RCK78[A:B]=(REFCLK/2). RXHR_xx = 0 on device reset. Receiver Power Down Control Bit, Channel xx. When PWRDNR_xx = 1, sections of the receive hardware are powered down to conserve power. PWRDNR_xx = 0 on device reset. Reserved. Set to 1 on device reset. Receive 8b/10b Decoder Enable Bit, Channel xx. When 8b10bR = 1, the 8b/10b decoder in the receive path is enabled. Otherwise, the data is passed undecoded. 8b10bR_xx = 0 on device reset. Link State Machine Enable Bit, Channel xx. When LINKSM_xx = 1, the receiver Fiber Channel link state machine is enabled. Otherwise, the Fibre Channel link state machine is disabled. Note: LINKSM_xx is ignored when XAUI_MODE_xx=1. LINKSM_xx = 0 on device reset. Not used.
[1]
PWRDNR_xx
[2] [3]
Reserved 8b10bR_xx
[4]
LINKSM_xx
[5:7] 30004 - AA 30014 - AB 30024 - AC 30034 - AD 30104 - BA 30114 - BB 30124 - BC 30134 - BD [0] [1]
Not used Reserved MASK_xx
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), xx=[AA,...,BD] See Reserved, must be set to 0. Set to 0 on device reset. bit Transmit and Receive Alarm Mask Bit, Channel xx. When MASK_xx = 1, descrip. the transmit and receive alarms of a channel are prevented from generating an interrupt (i.e., they are masked or disabled). The MASK_xx bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK_xx = 1 on device reset. Transmit and Receive Software Reset Bit, Channel xx. When SWRST_ss = 1, this bit provides the same function as the hardware reset, except that all configuration register settings are unaltered. This is not a self-clearing bit. Once set, this bit must be manually set and cleared. SWRST = 0 on device reset. Not used. 0 on reset. Transmit and Receive Test Enable Bit, Channel xx. When TESTEN_xx = 1, the transmit and receive sections are placed in test mode. The TestMode_[A:B][4:0] bits in the Global Control Registers specify the particular test, and must also be set. Note: When the global test enable bit GTESTEN_[A:B] = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN_[A:B] = 1, all channels are set to test mode regardless of their TESTEN setting. TESTEN_xx = 0 on device reset.
[2]
SWRST_xx
[3:6] [7]
Not used TESTEN_xx
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Lattice Semiconductor
Table 30. ORT82G5 Memory Map (Continued)
(0x) Absolute Address 30005 - A 30105 - B Reset Value (0x)
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0] [1]
Name Reserved GMASK_[A:B]
Description
SERDES Global Control Registers (Read Write) Act on all Four Channels in SERDES Quad A or SERDES Quad B. See Reserved, must be set to 0. Set to 0 on device reset. bit Global Mask. When GMASK_[A:B] = 1, the transmit and receive alarms descrip. of all channels in the SERDES quad are prevented from generating an interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit overrides the individual MASK_xx bits. GMASK_[A:B] = 1 on device reset. Software reset bit. The GSWRST_[A:B] bit provides the same function as the hardware reset for the transmit and receive sections of all four channels, except that the device configuration settings are not affected when GSWRST_[A:B] is asserted. This is not a self-clearing bit. Once set, this bit must be manually set and cleared. The GSWRST_[A:B] bit overrides the individual SWRST_xx bits. GSWRST_[A:B] = 0 on device reset. Powerdown Transmit Function. When GPWRDNT_[A:B] = 1, sections of the transmit hardware for all four channels of are powered down to conserve power. The GPWRDNT_[A:B] bit overrides the individual PWRDNT_xx bits. GPWRDNT_[A:B] = 0 on device reset. Powerdown Receive Function. When GPWRDNR_[A:B] = 1, sections of the receive hardware for all four channels are powered down to conserve power. The GPWRDNR_[A:B] bit overrides the individual PWRDNR_xx bits. GPWRDNR_[A:B] = 0 on device reset. Reserved, 1 on device reset. Not used. 0 on reset. Test Enable Control. When GTESTEN_[A:B] = 1, the transmit and receive sections of all four channels are placed in test mode. The GTESTEN_[A:B] bit overrides the individual TESTEN_xx bits. GTESTEN_[A:B] = 0 on device reset. 00 TestMode - See Test Mode section for settings Not used Reserved 00 ENBYSYNC_xx = 1 Enables Receiver Byte Synchronization for Channel xx. ENBYSYNC_xx = 0 on device reset.
[2]
GSWRST_[A:B]
[3]
GPWRDNT_[A:B]
[4]
GPWRDNR_[A:B]
[5] [6] [7]
Reserved Not used GTESTEN_[A:B]
30006 - A 30106 - B
[0:4] [5] [6:7]
TestMode[A:B] Not used Reserved ENBYSYNC_xx
Control Registers (Read/Write), xx=[AA,...,BD] 30800 - Ax 30900 - Bx [0]xA [1]xB [2]xC [3]xD [4]xA [5]xB [6]xC [7]xD 30801 - Ax 30901 - Bx [0]xA [1]xB [2]xC [3]xD [4]xA [5]xB [6]xC [7]xD
LCKREFN_xx
LCKREFN_xx = 0 Locks the receiver PLL to ref reference clock for Channel xx. LCKREFN_xx =1 = Locks the receiver to data for Channel xx. NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0. LCKREFN_xx = 0 on device reset. Enable Loopback Mode for Channel xx. When LOOPEN_xx=1, the transmitter high-speed output is looped back to the receiver high-speed input. This mode is similar to high-speed loopback mode enabled by TESTMODE_xx except that LOOPEN_xx disables the high-speed serial output. LOOPEN_xx=0 on device reset. Word Align Disable Bit. When NOWDALIGN_xx=1, receiver word alignment is disabled for Channel xx. NOWDALIGN_xx=0 on device reset.
LOOPENB_xx
NOWDALIGN_xx
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Lattice Semiconductor
Table 30. ORT82G5 Memory Map (Continued)
(0x) Absolute Address 30810 - Ax 30910 - Bx Reset Value (0x) 00
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0]xA [1]xB [2]xC [3]xD [4]xA [5]xB [6]xC [7]xD
Name DOWDALIGN_xx
Description Word Realign Bit. When DOWDALIGN_xx transitions from 0 to 1, the receiver realigns on the next comma character for Channel xx. NOWDALIGN_xx=0 on device reset. Enable multi-channel alignment for Channel xx. When FMPU_STR_EN_xx=1, the corresponding channel participates in multichannel alignment. FMPU_STR_EN_xx=0 on device reset.
FMPU_STR_EN _xx
30811 - Ax 30911 - Bx
[0:1] xA [2:3] xB [4:5] xC [6:7] xD [0]xA [1]xB [2]xC [3]xD
FMPU_SYNMOD E_xx[0:1]
00
Sync mode for xx 00 = No channel alignment 10 = Twin channel alignment 01 = Quad channel alignment 11 = Eight channel alignment
30820 - Ax 30920 - Bx
FMPU_RESYNC1 _xx
00
Resync a Single Channel. When FMPU_RESYNC1_xx transitions from 0 to 1, the corresponding channel is resynchronized (the write and read pointers are reset). FMPU_STR_EN_xx=0 on device reset. Resync a Pair of Channels. When FMPU_RESYNC2_[A:B][1:2] transitions from a 0 to a 1, the corresponding channel pair is resynchronized. FFMPU_RESYNC2_[A:B][1:2]=0 on device reset. Resync a Four-Channel Group. When FMPU_RESYNC4[A:B] transitions from a 0 to a 1, the corresponding four-channel group is resynchronized. FMPU_RESYNC4[A:B]=0 on device reset. Controls use of XAUI link state machine in place of Fibre-Channel state machine. When XAUI_MODE[A:B]=1, all four channels in the SERDES quad enable their XAUI link state machines. (LINKSM_xx bits are ignored). XAUI_MODE[A:B]=0 on device reset.
[4] FMPU_RESYNC2 xA & xB _x[1:2] [5] xC & xD [6] FMPU_RESYNC4 [A:B] XAUI_MODE[A:B]
[7]
30821 - A 30921 - B
[0]
NOCHALGN [A:B]
00
Bypass channel alignment. NOCHALGN [A:B] =1 causes bypassing of multi-channel alignment FIFOs for the corresponding SERDES quad. NOCHALGN [A:B] =0 on device reset.
[1:7] 30933 [0:3] [4:5]
Reserved for future use. Reserved for future use. SCHAR_CHAN[0: 1] 00 Select channel to test 00 = Channel BA 10 = Channel BB 01 =Channel BC 11 = Channel BD 1=Select TX option 0=Select RX option 1=Enable Characterization of SERDES B 00 XAUI Status Register. Status of XAUI link state machine for Channel xx 00 - No synchronization. 10 - Synchronization done. 11 - Not used. 01 - no_comma (see XAUI state machine) and at least one CV detected XAUISTAT_xx[0:1] = 00 on device reset.
[6] [7] 30804 - Ax 30904 - Bx [0:1] xA [2:3] xB [4:5] xC [6:7] xD
SCHAR_TXSEL SCHAR_ENA XAUISTAT_xx[0:1]
Status Registers (Read Only), xx=[AA,...,BD]
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Lattice Semiconductor
Table 30. ORT82G5 Memory Map (Continued)
(0x) Absolute Address 30805 - Ax 30905 - Bx Reset Value (0x) 00
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0]xA [1]xB [2]xC [3]xD [4]xA [5]xB [6]xC [7]xD
Name DEMUXWAS_xx
Description Status of Word Alignment. When DEMUX_WAS_xx=1, word alignment is achieved for Channel xx. DEMUX_WAS_xx=0 on device reset.
CH248_SYNC_xx
Status of Channel Alignment. When CH248_SYNC_xx=1, multi-channel alignment is achieved for Channel xx. CH248_SYNC_xx=0 on device reset. 00 Multi-Channel Overflow Status. When SYNC2_[A:B][1:2]OVFL=1, dualchannel synchronization FIFO overflow has occurred. SYNC2_[A:B][1:2]OVFL=0 on device reset. Multi-Channel Overflow Status. When SYNC4_[A:B]OVFL=1, quadchannel synchronization FIFO overflow has occurred. SYNC4_[A:B]OVFL=0 on device reset. Multi-Channel Out-Of-Sync Status. When SYNC2_[A:B][1:2] OOS=1, dual-channel synchronization has failed. SYNC2_[A:B][1:2] OOS=0 on device reset. Multi-Channel Out-Of-Sync Status. When SYNC4_[A:B]_OOS=1, quadchannel synchronization has failed. SYNC4_[A:B]_OOS=0 on device reset.
30814 - Ax 30914 - Bx
[0] SYNC2_[A:B][1:2] xA & AB OVFL [1] xC & xD [2] SYNC4_ [A:B]OVFL
[3] SYNC2_[A:B][1:2] xA & AB OOS [4] xC & xD [5] SYNC4_[A:B]_OO S Reserved for future use. TCKSELA 00
[6:7] 30A00 [0:1]
Common Control Registers (Read/Write) Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES quad A 00 = Channel AA 10 = Channel AB 01 = Channel AC 11 = Channel AD Receive Clock Select. Controls source of 78 MHz RCK78 for SEDRES quad A 00 = Channel AA 10 = Channel AB 01 = Channel AC 11 = Channel AD Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES quad B 00 = Channel BA 10 = Channel BB 01 = Channel BC 11 = Channel BD Receive Clock Select. Controls source of 78 MHz RCK78 for SERDES quad B 00 = Channel BA 10 = Channel BB 01 = Channel BC 11 = Channel BD 00 Reserved for future use LSb's for the threshold for low address in RX_FIFOs. RX_FIFO_MIN, Bit 5 is LSb. Useful values for RX_FIFO_MIN [0:4] are 0 to 17(decimal).
[2:3
RCKSELA
[4:5]
TCKSELB
[6:7]
RCKSELB
30A01
[0:4] [5:7]
-- RX_FIFO_MIN
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Lattice Semiconductor
Table 30. ORT82G5 Memory Map (Continued)
(0x) Absolute Address 30A02 Reset Value (0x) 00
ORCA ORT42G5 and ORT82G5 Data Sheet
Bit [0:1] [2] [3:7]
Name RX_FIFO_MIN FMPU_RESYNC8 -- SYNC8_OVFL
Description MSb's for the threshold for low address in RX_FIFOs. RX_FIFO_MIN, Bit 1 is MSb. Useful values for RX_FIFO_MIN [0:4] are 0 to 17(decimal). Resynchronizes all 8 channels when it transitions from 0 to 1. Status is a 0 on device reset. Reserved for future use.
Common Status Registers xx=[AA,...,BD] 30A03 [0] 00 Read-Only Multi-Channel Overflow Status. When SYNC8_OVFL=1, 8-channel synchronization FIFO overflow has occurred. SYNC8_OVFL=0 on device reset. Read-Only Multi-Channel Out-Of-Sync Status. When SYNC8_OOS=1, 8-channel synchronization has failed. SYNC8_OOS=0 on device reset.
[1] [2:7]
SYNC8_OOS Reserved for future use.
Recommended Board-level Clocking for the ORT42G5 and ORT82G5
Option 1: Asynchronous Reference Clocks Between Rx and Tx Devices Each board that uses the ORT42G5 or ORT82G5 as a transmit or receive device will have its own local reference clock as shown in Figure 37. Figure 37 shows the ORT82G5 device on the switch card receiving data on two of its channels from a separate source. Data tx1 is transmitted from a tx device with refclk1 as the reference clock and Data tx2 is transmitted from a tx device with refclk2 as the reference clock. Receive channel AA locks to the incoming data tx1 and receive channel AB locks to the incoming data tx2. The advantage of this clocking scheme is the fact that it is not necessary to distribute a reference clock (typically 156 MHz for 10GE and 155.52 MHz for OC-192 applications) across a backplane. Figure 37. Asynchronous Clocking Between Rx and Tx Devices
BACKPLANE PORT CARD #1 REFCLK 1 ORT42G5 or ORT82G5 TX2 PORT CARD #2 REFCLK 2 ORT42G5 or ORT82G5 TX1 AC REFCLK 3 AD ORT42G5 or ORT82G5
SWITCH CARD
Option 2: Synchronous Reference Clocks to Rx and Tx Devices In this type of clocking, a single reference clock is distributed to all receive and transmit devices in a system (Figure 38). This distributed clocking scheme will permit maximum flexibility in the usage of transmit and receive channels in the current silicon such as: * All transmit and receive channels can be used within any quad in receive channel alignment or alignment bypass mode. * In channel alignment mode, each receive channel operates on its own independent clock domain.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
The disadvantage with this scheme is the fact that it is difficult to distribute a 156 MHz reference clock across a backplane. This may require expensive clock driver chips on the board to drive clocks to different destinations within the specified jitter limits for the reference clock. Figure 38. Distributed Reference Clock to Rx And Tx Devices
REFCLK BACKPLANE PORT CARD #1 TX1 ORT42G5 or ORT82G5 TX2 PORT CARD #2 ORT42G5 or ORT82G5 AC ORT42G5 or ORT82G5 SWITCH CARD
AD
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. The ORCA Series 4 FPSCs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress.
Parameter Storage Temperature Symbol TSTG VDD33 Power Supply Voltage with Respect to Ground VDDIO VDD15, VDD_ANA, VDDGB Input Signal with Respect to Ground Signal Applied to High-impedance Output Maximum Package Body (Soldering) Temperature VIN -- -- Min. - 65 - 0.3 - 0.3 -- VSS - 0.3 VSS - 0.3 -- Max. 150 4.2 4.2 2.0 VDDIO + 0.3 VDDIO + 0.3 220 Unit C V V V V V C
Recommended Operating Conditions
Parameter Power Supply Voltage with Respect to Ground1 Input Voltages Junction Temperature SERDES Supply Voltage SERDES CML I/O Supply Voltage Symbol VDD33 VDD15 VIN TJ VDD_ANA, VDDGB VDDIB, VDDOB Min. 3.0 1.425 VSS - 0.3 - 40 1.425 1.425 Max. 3.6 1.575 VDDIO + 0.3 125 1.575 1.89 Unit V V V C V V
1. For FPGA Recommended Operating Conditions and Electrical Characteristics, see the Recommended Operating Conditions and Electrical Characteristics tables in the ORCA Series 4 FPGA data sheet (OR4E04) and the ORCA Series 4 I/O Buffer Technical Note. FPSC Standby Currents (IDDSB15 and IDDSB33) are tested with the Embedded Core in the powered down state.
SERDES Electrical and Timing Characteristics
Table 31. Absolute Maximum Ratings
Parameter ORT82G5 Power Dissipation Conditions SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 1.25 Gbit/s SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 2.50 Gbit/s SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 3.125 Gbit/s 8b/10b Encoder/Decoder (per Channel) SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 1.25 Gbit/s SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 2.50 Gbit/s SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 3.125 Gbit/s 8b/10b Encoder/Decoder (per Channel) Max.1 195 210 225 50 265 275 295 50 Units mW mW mW mW mW mW mW mW
ORT42G5 Power Dissipation
1. With all channels operating, 1.575V supply.
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Lattice Semiconductor High Speed Data Transmitter
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 32 specifies serial data output buffer parameters measured on devices with typical and worst case process parameters and over the full range of operation conditions. Table 32. Serial Output Timing and Levels (CML I/O)
Parameter Rise Time (20%--80%) Fall Time (80%--20%) Common Mode Differential Swing (Full Amplitude)1 Differential Swing (Half Amplitude)1 Output Load (external) Min. 50 50 VDDOB - 0.30 600 300 -- Typ. 80 80 VDDOB - 0.25 700 350 86 Max. 110 110 VDDOB - 0.15 1000 500 -- Units ps ps V mVp-p mVp-p
1. Differential swings measured at the end of 3 inches of FR-4 and 12 inches of coax cable.
Transmitter output jitter is a critical parameter to systems with high speed data links. Table 33 and Table 34 specify the transmitter output jitter for typical and worst case devices over the full range of operating conditions. Table 33. Channel Output Jitter (3.125 Gbps)
Parameter Deterministic Random Total2, 3 Device ORT42G5 ORT82G5 ORT42G5 ORT82G5 ORT42G5 ORT82G5 Min. -- -- -- -- -- -- Typ.1 0.12 0.12 0.05 0.05 0.17 0.17 Max.1 0.21 0.16 0.10 0.08 0.31 0.24 Units Ulp-p Ulp-p Ulp-p Ulp-p Ulp-p Ulp-p
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., 0 oC to 85oC, 1.425V to 1.575V supply. 2. Wavecrest SIA-3000 instrument used to measure one-sigma (rms) random jitter component value. This value is multiplied by 14 to provide the peak-to-peak value that corresponds to a BER of 10-12. 3. Total jitter measurement performed with Wavecrest SIA-3000 at a BER of 10-12. See instrument documentation and other Wavecrest publications for a detailed discussion of jitter types included in this measurement.
Table 34. Channel Output Jitter (2.5 Gbps)
Parameter Deterministic Random Total2, 3 Device ORT42G5 ORT82G5 ORT42G5 ORT82G5 ORT42G5 ORT82G5 Min. -- -- -- -- -- -- Typ.1 0.11 0.11 0.05 0.05 0.16 0.16 Max.1 0.13 0.13 0.14 0.07 0.27 0.20 Units Ulp-p Ulp-p Ulp-p Ulp-p Ulp-p Ulp-p
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., 0 oC to 85oC, 1.425V to 1.575V supply. 2. Wavecrest SIA-3000 instrument used to measure one-sigma (rms) random jitter component value. This value is multiplied by 14 to provide the peak-to-peak value that corresponds to a BER of 10-12. 3. Total jitter measurement performed with Wavecrest SIA-3000 at a BER of 10-12. See instrument documentation and other Wavecrest publications for a detailed discussion of jitter types included in this measurement.
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Lattice Semiconductor High Speed Data Receiver
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 35 specifies receiver parameters measured on devices with worst case process parameters and over the full range of operation conditions. Table 35. External Data Input Specifications
Parameter Input Data Stream of Nontransitions Sensitivity (differential), worst-case Input Levels2 Internal Buffer Resistance (Each input to VDDIB) PLL Lock Time3
1
Conditions 8b/10b encode/decode off 3.125 Gbps -- -- --
Min. -- 80 VSS - 0.3 40 --
Typ. -- -- -- 50 --
Max. 72 -- VDD_ANA + 0.3 60 Note 2
Units Bits mVp-p V --
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0oC to 85oC, 1.425V to 1.575V supply. 2. Input level min + (input peak to peak swing)/2 common mode input voltage input level max - (input peak to peak swing)/2 3. The ORT42G5 and ORT82G5 SERDES receiver performs four levels of synchronization on the incoming serial data stream, providing first bit, then byte (character), then channel (32-bit word), and finally optional multi-channel alignment as described in TN1025. The PLL Lock Time is the time required for the CDR PLL to lock to the transitions in the incoming high-speed serial data stream. If the PLL is unable to lock to the serial data stream, it instead locks to REFCLK to stabilize the voltage-controlled oscillator (VCO), and periodically switches back to the serial data stream to again attempt synchronization.
Input Data Jitter Tolerance A receiver's ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface standards have recognized the dependency on jitter type and have recently modified specifications to indicate tolerance levels for different jitter types as they relate to specific protocols (e.g XAUI, FC, Infiniband etc.). Sinusoidal jitter is considered to be a worst case jitter type. Table 36 shows receiver specifications with 10 MHz sinusoidal jitter injection. XAUI specific jitter tolerance measurements were measured in a separate experiment detailed in technical note TN1032, SERDES Test Chip Jitter, and are not reflected in these results. Table 36. Receiver Sinusoidal Jitter Tolerance Specifications
Parameter Input Data Jitter Tolerance @3.125Gbps, Typical Jitter Tolerance @3.125Gbps, Worst case Jitter Tolerance @2.5Gbps,Typical Jitter Tolerance @2.5Gbps, Worst case 600 mV diff eye1 600 mV diff eye 600 mV diff eye
1
Conditions
Max. 0.75 0.65 0.79 0.67
Unit UIP-P UIP-P UIP-P UIP-P
600 mV diff eye1
1
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0oC to 85oC, 1.425V to 1.575V supply. Jitter measured with a Wavecrest SIA-3000.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Input Eye-Mask Characterization Figure 39. provides an eye-mask characterization of the SERDES receiver input. The eye-mask is specified below for two different eye-mask heights. It provides guidance on a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Almost all detrimental characteristics of transmit signal and the interconnection link design result in eye-closure. This, combined with the eyeopening limitations of the line receiver, can provide a good indication of a link's ability to transfer data error-free. The Clock and Data Recovery (CDR) portion of the ORT42G5 and ORT82G5 SERDES receiver has the ability to filter incoming signal jitter that is below the clock recovery PLL bandwidth (about 3 MHz). The eye-mask specifications of Table 37 are for jitter frequencies above the PLL bandwidth of the CDR, which is a worst case condition. When jitter occurs at frequencies below the PLL bandwidth, the receiver jitter tolerance is significantly better. For this case error-free data detection can occur even with a completely closed eye-mask. Figure 39. Receive Data Eye-Diagram Template (Differential)
T
1.2V
V
H
UI
Table 37. Receiver Eye-Mask Specifications1
Parameter Input Data Eye Opening Width (H)@ 3.125Gbps Eye Opening Width (T)@ 3.125Gbps Eye Opening Width (H)@ 3.125Gbps Eye Opening Width (T)@ 3.125Gbps Eye Opening Width (H)@ 2.5Gbps Eye Opening Width (T)@ 2.5Gbps Eye Opening Width (H)@ 2.5Gbps Eye Opening Width (T)@ 2.5Gbps V=175 mV diff1 V=175 mV diff1 V=600 mV diff V=175 mV diff V=600 mV diff
1
Conditions
Value 0.55 0.15 0.35 0.10 0.42 0.15 0.33 0.10
Unit UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P
V=600 mV diff1
1
V=175 mV diff1
1
V=600 mV diff1
1. With PRBS 2^7-1 data pattern, 10 MHz sinusoidal jitter, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0oC to 85oC, 1.425V to 1.575V supply.
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Lattice Semiconductor External Reference Clock
ORCA ORT42G5 and ORT82G5 Data Sheet
The external reference clock selection and its interface are a critical part of system applications for this product. Table 38 specifies reference clock requirements, over the full range of operating conditions. The designer is encourage to read TN1040, SERDES Reference Clock, which discusses various aspects of this system element and its interconnection. Table 38. Reference Clock Specifications (REFCLKP and REFCLKN)
Parameter Frequency Range Frequency Tolerance1 Duty Cycle (Measured at 50% Amplitude Point) Rise Time Fall Time P-N Input Skew Differential Amplitude Common Mode Level Single-Ended Amplitude Input Capacitance (at REFCLKP) Input Capacitance (at REFCLKN) Min. 60 -350 40 -- -- -- 500 Vsingle-ended/2 250 -- -- Typ. -- -- 50 500 500 -- 800 0.75 400 -- -- Max. 185 350 60 1000 1000 75 2 x VDDIB VDD15 - (Vsingle-ended/2) VDDIB 5 5 Units MHz ppm % ps ps ps mVp-p V mVp-p pF pF
1. This specification indicates the capability of the high speed receiver CDR PLL to acquire lock when the reference clock frequency and incoming data rate are not synchronized.
Embedded Core Timing Characteristics
Table 39 summarizes the end-to-end latencies through the embedded core for the various modes. All latencies are given in clock cycles for system clocks at half the REFCLK_[A:B] frequency. For a REFCLK_[A:B] of 156.25 MHz, a system clock cycle is 6.4 ns. Table 39. Signal Latencies, Embedded Core
Operating Mode Transmit Path Receive Path Multi-Channel Alignment Bypassed1 With Multi-Channel Alignment1 4.5 clock cycles 13.5-22.5 clock cycles Signal Latency (max.) 5 clock cycles
1. With multi-channel alignment, the latency is largest when the skew between channels is at the maximum that can be correctly compensated for (18 clock cycles). The latency specified in the table is for data from the channel received first.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Pin Descriptions
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-programmable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor. If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor after configuration. The pin descriptions in Table and throughout this data sheet show active-low signals with an overscore. The package pinout tables that follow, show this as a signal ending with _N. For example LDC and LDC_N are equivalent. Table 40. Pin Descriptions
Symbol Dedicated Pins VDD33 VDD15 VDDIO VSS PTEMP RESET O CCLK I -- 3.3V positive power supply. This power supply is used for 3.3V configuration RAMs and internal PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on the board for proper operation. -- 1.5V positive power supply for internal logic. -- Positive power supply used by I/O banks. -- Ground. I I Temperature sensing diode pin. Dedicated input. During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset. In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration data in. In the slave or readback after configuration, CCLK is input synchronous with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. As an input, a low level on DONE delays FPGA start-up after configuration.1 As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has an optional pull-up resistor.
PRGRM is an active-low input that forces the restart of configuration and resets the boundaryscan circuitry. This pin always has an active pull-up.
I/O
Description
I DONE O I I RD_CFG
PRGRM
This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0. RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary-scan, TDO is test data out. During JTAG, slave, master, and asynchronous peripheral configuration assertion on this CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low interrupt request output, when the MPI is used.
RD_DATA/TDO CFG_IRQ/MPI_IRQ LVDS_R Special-Purpose Pins
O O
-- Reference resistor connection for controlled impedance termination of Series 4 FPGA LVDS inputs. I During powerup and initialization, M0--M3 are used to select the configuration mode with their values latched on the rising edge of INIT. During configuration, a pull-up is enabled. Semi-dedicated PLL clock pins. During configuration they are 3-stated with a pull up. Pins dedicated for the primary clock. Input pins on the middle of each side with differential pairing.
M[3:0] I I P[TBLR]CLK[1:0][TC]
I/O After configuration, these pins are user-programmable I/O.1 PLL_CK[0:7][TC] I/O These pins are user-programmable I/O pins if not used by PLLs after configuration.
I/O After configuration these pins are user programmable I/O, if not used for clock inputs.
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Lattice Semiconductor
Table 40. Pin Descriptions (Continued)
Symbol I/O I TDI, TCK, TMS
ORCA ORT42G5 and ORT82G5 Data Sheet
Description If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If boundary-scan is not selected, all boundary-scan functions are inhibited once configuration is complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled during configuration. During configuration in asynchronous peripheral mode, RDY/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used. High During Configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete.
Low During Configuration is output low until configuration is complete. It is used as a control output, indicating that configuration is not complete.
I/O After configuration, these pins are user-programmable I/O if boundary scan is not used.1 O RDY/BUSY/RCLK
I/O After configuration this pin is a user-programmable I/O pin.1 O HDC O LDC
I/O After configuration, this pin is a user-programmable I/O pin.1
I/O After configuration, this pin is a user-programmable I/O pin.1 I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before the start of configuration. After configuration, this pin is a user-programmable I/O pin.1 I CS0, CS1
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-up is enabled. RD is used in the asynchronous peripheral configuration mode. A low on RD changes D[7:3] into a status output. WR and RD should not be used simultaneously. If they are, the write strobe overrides. This pin is also used as the MPI data transfer strobe. As a status indication, a high indicates ready, and a low indicates busy.
INIT
I/O After configuration, if MPI is not used, these pins are user-programmable I/O pins.1 I RD/MPI_STRB
I WR/MPI_RW
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the FPGA. In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write transfer to the FPGA. During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus master utilizing the least-significant bits of the PowerPC 32-bit address. MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high indicates that the current transfer is not a burst. MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word. During master parallel mode A[21:0] address the configuration EPROMs up to 4M bytes. In MPI mode this is driven low indicating the MPI received the data on the write cycle or returned data on a read cycle.
I/O After configuration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.1 PPC_A[14:31] MPI_BURST MPI_BDIP MPI_TSZ[0:1] A[21:0] I O O MPI_ACK I I I
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1
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Lattice Semiconductor
Table 40. Pin Descriptions (Continued)
Symbol I/O I MPI_CLK
ORCA ORT42G5 and ORT82G5 Data Sheet
Description This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a source of the clock for the Embedded System Bus. If MPI is used this will be the AMBA bus clock. A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal system bus for the current transaction. This pin requests the MPC860 to relinquish the bus and retry the cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1 O MPI_TEA O
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1 MPI_RTRY I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1 I/O Selectable data bus width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write transaction and driven by MPI in a read transaction. I D[0:31] O D[7:0] receive configuration data during master parallel, peripheral, and slave parallel configuration modes when WR is low and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. D[7:3] output internal status for asynchronous peripheral mode when RD is low.
I/O After configuration, if MPI is not used, the pins are user-programmable I/O pins.1 DP[0:3] I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for D[16:23], and DP[3] for D[24:31]. After configuration, if MPI is not used, the pins are user-programmable I/O pin.1 I DIN During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a pull-up is enabled. During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave devices. Data out on DOUT changes on the rising edge of CCLK.
I/O After configuration, this pin is a user-programmable I/O pin.1 O DOUT
TESTCFG (ORT82G5 only)
1 I/O After configuration, DOUT is a user-programmable I/O pin. I During configuration this pin should be held high, to allow configuration to occur. A pull up is enabled during configuration.
I/O After configuration, TESTCFG is a user programmable I/O pin.1
1. The FPGA States of Operation section in the ORCA Series 4 FPGAs data sheet (ORT82G5 only) contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
This section describes device I/O signals to/from the embedded core. Table 41. FPSC Function Pin Descriptions
Symbol I/O I I I I I I I I I O I I I I -- -- -- -- REXTN_B HDINN_AA (ORT82G5 only) HDINP_AA (ORT82G5 only) HDINN_AB (ORT82G5 only) HDINP_AB (ORT82G5 only) HDINN_AC HDINP_AC HDINN_AD HDINP_AD HDINN_BA (ORT82G5 only) HDINP_BA (ORT82G5 only) HDINN_BB (ORT82G5 only) HDINP_BB (ORT82G5 only) HDINN_BC HDINP_BC HDINN_BD HDINP_BD SERDES quad A and B Pins HDOUTN_AA (ORT82G5 only) HDOUTP_AA (ORT82G5 only) HDOUTN_AB (ORT82G5 only) O O O High-speed CML transmit data output - SERDES quad A, channel A. High-speed CML transmit data output - SERDES quad A, channel A. High-speed CML transmit data output - SERDES quad A, channel B. I I I I I I I I I I I I I I I I Description Active low reset for the embedded core. All non-SERDES specific registers (addresses 308***, 309***, 30A***) in the embedded core are not reset.1 Active low 3-state for embedded core output buffers.1 Active low power down of all SERDES blocks and associated I/Os.1 Clock input for BIST and loopback test.1 Selection of PASB_TESTCLK input for BIST test.1 Selection of PASB_TESTCLK input for loopback test.1 Clock input for microprocessor in test mode.1 Selection of PMP_TESTCLK in test mode.1 Input to start BIST test.1 Output result of BIST test. CML reference clock input--SERDES quad A. CML reference clock input--SERDES quad A. CML reference clock input--SERDES quad B. CML reference clock input--SERDES quad B. Reference resistor - SERDES quad A. Reference resistor - SERDES quad B. Reference resistor - SERDES quad -. A 3.32 K W 1% resistor must be connected across REXT_B and REXTN_B. This resistor should handle a current of 300 A. Reference resistor - SERDES quad B. A 3.32 K 1% resistor must be connected across REXT_B and REXTN_B. This register should handle a current of 300 A High-speed CML receive data input - SERDES quad A, channel A. High-speed CML receive data input - SERDES quad A, channel A. High-speed CML receive data input - SERDES quad A, channel B. High-speed CML receive data input - SERDES quad A, channel B. High-speed CML receive data input - SERDES quad A, channel C. High-speed CML receive data input - SERDES quad A, channel C. High-speed CML receive data input - SERDES quad A, channel D. High-speed CML receive data input - SERDES quad A, channel D. High-speed CML receive data input - SERDES quad B, channel A. High-speed CML receive data input - SERDES quad B, channel A. High-speed CML receive data input - SERDES quad B, channel B. High-speed CML receive data input - SERDES quad B, channel B. High-speed CML receive data input - SERDES quad B, channel C. High-speed CML receive data input - SERDES quad B, channel C. High-speed CML receive data input - SERDES quad B, channel D. High-speed CML receive data input - SERDES quad B, channel D. Common Signals for Both SERDES Quad A and B PASB_RESETN PASB_TRISTN PASB_PDN PASB_TESTCLK PBIST_TEST_ENN PLOOP_TEST_ENN PMP_TESTCLK PMP_TESTCLK_ENN PSYS_DOBISTN PSYS_RSSIG_ALL SERDES Quad A and B Pins REFCLKN_A REFCLKP_A REFCLKN_B REFCLKP_B REXT_A REXT_B REXTN_A
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Lattice Semiconductor
Table 41. FPSC Function Pin Descriptions (Continued)
Symbol HDOUTP_AB (ORT82G5 only) HDOUTN_AC HDOUTP_AC HDOUTN_AD HDOUTP_AD HDOUTN_BA (ORT82G5 only) HDOUTP_BA (ORT82G5 only) HDOUTN_BB (ORT82G5 only) HDOUTP_BB (ORT82G5 only) HDOUTN_BC HDOUTP_BC HDOUTN_BD HDOUTP_BD Power and Ground VDDIB_AA (ORT82G5 only) VDDIB_AB (ORT82G5 only) VDDIB_AC VDDIB_AD VDDIB_BA (ORT82G5 only) VDDIB_BB (ORT82G5 only) VDDIB_BC VDDIB_BD VDDOB_AA (ORT82G5 only) VDDOB_AB (ORT82G5 only) VDDOB_AC VDDOB_AD VDDOB_BA (ORT82G5 only) VDDOB_BB (ORT82G5 only) VDDOB_BC VDDOB_BD VDDGB_A VDDGB_B VDD_ANA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O O O O O O O O O O O O O O
ORCA ORT42G5 and ORT82G5 Data Sheet
Description High-speed CML transmit data output - SERDES quad A, channel B. High-speed CML transmit data output - SERDES quad A, channel C. High-speed CML transmit data output - SERDES quad A, channel C. High-speed CML transmit data output - SERDES quad A, channel D. High-speed CML transmit data output - SERDES quad A, channel D. High-speed CML transmit data output - SERDES quad B, channel A. High-speed CML transmit data output - SERDES quad B, channel A. High-speed CML transmit data output - SERDES quad B, channel B. High-speed CML transmit data output - SERDES quad B, channel B. High-speed CML transmit data output - SERDES quad B, channel C. High-speed CML transmit data output - SERDES quad B, channel C. High-speed CML transmit data output - SERDES quad B, channel D. High-speed CML transmit data output - SERDES quad B, channel D. 1.8V/1.5V power supply for high-speed serial input buffers. 1.8V/1.5V power supply for high-speed serial input buffers. 1.8V/1.5V power supply for high-speed serial input buffers. 1.8V/1.5V power supply for high-speed serial input buffers. 1.8V/1.5V power supply for high-speed serial input buffers. 1.8V/1.5V power supply for high-speed serial input buffers. 1.8V/1.5V power supply for high-speed serial input buffers. 1.8V/1.5V power supply for high-speed serial input buffers. 1.8V/1.5V power supply for high-speed serial output buffers. 1.8V/1.5V power supply for high-speed serial output buffers. 1.8V/1.5V power supply for high-speed serial output buffers. 1.8V/1.5V power supply for high-speed serial output buffers. 1.8V/1.5V power supply for high-speed serial output buffers. 1.8V/1.5V power supply for high-speed serial output buffers. 1.8V/1.5V power supply for high-speed serial output buffers. 1.8V/1.5V power supply for high-speed serial output buffers. 1.5V guard band power supply. 1.5V guard band power supply. 1.5V power supply for SERDES analog receive and transmit circuitry.
1. Should be externally connected on board to 3.3V pull-up resistor.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Power Supplies for ORT42G5 AND ORT82G5
Power Supply Descriptions
Table shows the ORT42G5 and ORT82G5 FPGA and embedded core power supply groupings. VDD33 Is a 3.3V positive power supply used for 3.3V configuration RAMs and internal PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on the board for proper operation. The five VDDIO supplies are positive power supply used by the FPGA I/O banks.The 1.5 volt digital power supplies are used for the FPGA and the embedded core transmit and receive digital logic including the microprocessor logic. The 1.5 volt analog power supply is used for high-speed analog circuitry in the embedded core between the I/O buffers and the digital logic. The RX input buffer power supplies are used to power the input (receive) buffers. The TX output buffer supplies are used to power the output (transmit) buffers. The Rx and TX buffer power supplies can be independently set to 1.5V or 1.8V, depending on the end application. The guard band supplies are independent connection brought out to pins. Table 42. Power Supplies
FPGA and Core Digital Supply 1.5V VDD15 -- -- -- -- -- -- --
1. ORT82G5 only.
FPGA Supplies VDD33 VDDIO0 VDDIO1 VDDIO5 VDDIO6 VDDIO7
Analog 1.5V VDD_ANA
Tx Output Buffers 1.5V/1.8V (VDDOB) VDDOB_AA1 VDDOB_AB
1
Rx Input Buffers 1.5V/1.8V (VDDIB) VDDIB_AA1 VDDIB_AB1 VDDIB_AC VDDIB_AD VDDIB_BA
1
Guard Band 1.5V (VDDGB) VDDGB_A VDDGB_B -- -- -- -- -- --
VDDOB_AC VDDOB_AD VDDOB_BA
1
VDDOB_BB1 VDDOB_BC VDDOB_BD
VDDIB_BB1 VDDIB_BC VDDIB_BD
Recommended Power Supply Connections
Ideally, a board should have the power supplies described below: * VDD33 and VDDIO supplies for the FPGA Logic * A single 1.5V source to supply power to FPGA and core digital logic. * A dedicated 1.5V power supply for the analog power pins. This will allow the end user to minimize noise. The guard band pins can also be sourced from the analog power supplies. * TX output buffer power. The power supplies to the TS output buffers should be isolated from the rest of the board power supplies. Special care must be taken to minimize noise when providing board level power to these output buffers. The power supply can be 1.5V or 1.8V depending on the end application. * RX input buffer power. The power supplies to the Rx input buffers should be isolated from the rest of the board power supplies. Special care must be taken to minimize noise when providing board level power to these input buffers. The power supply can be 1.5V or 1.8V depending on the end application.
Recommended Power Supply Filtering Scheme
The board connections of the various SERDES VDD and VSS pins are critical to system performance. An example demonstration board schematic is available at www.latticesemi.com. Power supply filtering is in the form of: * A parallel bypass capacitor network consisting of 10 f, 0.1 f, and 1.0 f caps close to the power source. * A parallel bypass capacitor network consisting of 0.01 f and 0.1 f close to the pin on the ORT42G5. 85
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
* Example connections are shown in Figure 40. The naming convention for the power supply sources shown in the figure are as follows: - Supply_1.5V - Tx-Rx digital, auxiliary power pins. - Supply_VDDIB - Input Rx buffer power pins. - Supply_VDDOB - Output Tx buffer power pins. - Supply_VDDANA - Tx analog power pins, Rx analog power pins, guard band power pins. Figure 40. Power Supply Filtering
SOURCE SUPPLY_1.5 V VDD15 0.1 f 4.7 H PIN
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS SUPPLY_VDD Analog 4.7 H VDD_ANA
0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS --1 EACH FOR VDDGB_[A,B] SUPPLY_VDDIB 4.7 H VDDIB
0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS SUPPLY_VDDOB 4.7 H VDDOB
0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS
86
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Package Information
Package Pinouts
Table 43 provides the number of user-programmable I/Os available for each package. Table 43. I/O Summary
Device User programmable I/O Available programmable differential pair pins FPGA configuration pins FPGA dedicated function pins Core function pins VDD15 VDD33 VDDIO VSS VDDGB VDDIB VDDOB VDD_ANA No connect Total package pins ORT42G5 204 166 7 2 32 49 8 34 112 2 4 8 22 0 484 ORT82G5 372 330 7 2 71 63 10 32 91 2 8 12 8 2 680
Table 44 and Table 45 provide the package pin and pin function for the ORT42G5 and ORT82G5 FPSC and packages. The bond pad name is identified in the PIO nomenclature used in the ispLEVER System software design editor. The Bank column provides information as to which output voltage level bank the given pin is in. The Group column provides information as to the group of pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then the VREF pin is available as an I/O pin. When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for the FPGA. The tables provide no information on unused pads. As shown in the pair columns in Table 38, differential pairs and physical locations are numbered within each bank (e.g., L19C-A0 is the nineteenth pair in an associated bank). A `C' indicates complementary differential, whereas a `T' indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or vertical direction. Other physical indicators are as follows: * _A1 indicates one ball between pairs. * _A2 indicates two balls between pairs. * _D0 indicates balls are diagonally adjacent. * _D1 indicates balls are diagonally adjacent, separated by one physical ball. VREF pins, shown in the Pin Description columns in Table 44 and Table 45, are associated to the bank and group (e.g., VREF_TL_01 is the VREF for group one of the Top Left (TL) bank.
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Lattice Semiconductor
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout
484-PBGAM VDDIO Bank E4 C20 D3 F5 F4 C2 C1 F3 A1 D2 D1 E7 E2 E1 G3 G4 F2 F1 G2 G1 E8 A2 H1 H2 E5 H4 H3 J1 J2 J4 G7 J3 K6 K1 K2 K3 K4 G8 F8 K5 L1 L2 L6 F9 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) VREF Group 7 7 7 7 7 8 8 8 9 9 9 9 9 10 10 10 10 1 1 1 2 2 2 3 3 4 4 4 I/O O VDD15 I I I IO IO IO VSS IO IO VDDIO0 IO IO IO IO IO IO IO IO VDDIO0 VSS IO IO VDD15 IO IO IO IO IO VSS IO VDDIO7 IO IO IO IO VSS VDD15 IO IO IO VDDIO7 VDD15
ORCA ORT42G5 and ORT82G5 Data Sheet
Pin Description PRD_DATA VDD15 PRESET_N PRD_CFG_N PPRGRM_N PL2D PL2C PL3C VSS PL4D PL4C VDDIO0 PL5D PL5C PL5A PL6C PL7D PL7C PL8D PL8C VDDIO0 VSS PL10D PL10C VDD15 PL11D PL11C PL12D PL12C PL13C VSS PL14D VDDIO7 PL15D PL15C PL16C PL17D VSS VDD15 PL19D PL20D PL20C VDDIO7 VDD15
Additional Function RD_DATA/TDO RESET_N RD_CFG_N PRGRM_N PLL_CK0C/HPPLL PLL_CK0T/HPPLL VREF_0_07 D5 D6 HDC LDC_N D7 VREF_0_09 A17/PPC_A31 CS0_N CS1 INIT_N DOUT VREF_0_10 A16/PPC_A30 A15/PPC_A29 A14/PPC_A28 D4 RDY/BUSY_N/RCLK A13/PPC_A27 A12/PPC_A26 A11/PPC_A25 RD_N/MPI_STRB_N PLCK0C PLCK0T -
484-PBGAM L1C L1T L2C L2T L3C L3T L4C L4T L5C L5T L6C L6T L7C L7T L8C L8T L9C L9T -
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank G9 L3 L4 L5 F10 G10 M3 M4 N4 M2 M1 N3 F11 N5 M5 N2 N1 G11 P2 P1 F12 P3 P4 R4 R3 R2 R1 G12 T3 P5 T2 T1 U1 U2 R5 V1 V2 G13 W2 W1 Y1 Y2 U3 F13 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) VREF Group 5 5 5 6 6 6 6 6 7 8 8 8 8 8 8 8 1 1 1 1 2 2 2 3 3 3 3 4 4 4 4 I/O VSS IO IO IO VDD15 VSS IO IO IO IO IO IO VDD15 IO VDDIO7 IO IO VSS IO IO VDD15 IO IO IO IO IO IO VSS IO VDDIO6 IO IO IO IO VDDIO6 IO IO VSS IO IO IO IO I VDD15 Pin Description VSS PL21D PL21C PL22D VDD15 VSS PL24D PL24C PL25C PL26D PL26C PL27D VDD15 PL28D VDDIO7 PL29D PL29C VSS PL30D PL30C VDD15 PL31D PL31C PL32D PL32C PL33D PL33C VSS PL34D VDDIO6 PL34B PL34A PL35B PL35A VDDIO6 PL36B PL36A VSS PL37B PL37A PL39D PL39C PTEMP VDD15 Additional Function A10/PPC_A24 A9/PPC_A23 A8/PPC_A22 PLCK1C PLCK1T A7/PPC_A21 A6/PPC_A20 A5/PPC_A19 WR_N/MPI_RW A4/PPC_A18 A3/PPC_A17 A2/PPC_A16 A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 D9 D10 D11 D12 VREF_6_03 D13 VREF_6_04 PLL_CK7C/HPPLL PLL_CK7T/HPPLL PTEMP 484-PBGAM L10C L10T L11C L11T L12C L12T L13C L13T L14C L14T L15C L15T L16C L16T L17C L17T L18C L18T L19C L19T L20C L20T L21C L21T L22C L22T -
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank V4 V3 F17 W3 AA2 AB2 AA3 AB3 T5 H7 Y4 W4 T8 AA4 AB4 H8 W5 Y5 T9 AA5 AB5 H9 V6 G6 W6 Y6 H10 AA6 AB6 U6 W7 Y7 H11 V7 U7 AA7 AB7 V8 H12 W8 Y8 U8 AA8 AB8 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) VREF Group 5 5 5 5 5 6 6 7 7 7 7 7 7 8 8 8 9 9 9 9 10 10 10 11 11 11 11 11 11 I/O IO VDD33 VDD15 IO IO IO IO IO VDDIO6 VSS IO IO VDDIO6 IO IO VSS IO IO VDDIO6 IO IO VSS IO VDD15 IO IO VSS IO IO VDDIO6 IO IO VSS IO VDDIO6 IO IO IO VSS IO IO IO IO IO Pin Description LVDS_R VDD33 VDD15 PB2A PB2C PB2D PB4A PB4B VDDIO6 VSS PB5C PB5D VDDIO6 PB6C PB6D VSS PB7C PB7D VDDIO6 PB8C PB8D VSS PB9C VDD15 PB10C PB10D VSS PB11C PB11D VDDIO6 PB12C PB12D VSS PB14A VDDIO6 PB14C PB14D PB15A VSS PB15C PB15D PB16A PB16C PB16D Additional Function LVDS_R DP2 PLL_CK6T/PPLL PLL_CK6C/PPLL VREF_6_05 DP3 VREF_6_06 D14 D15 D16 D17 D18 VREF_6_07 D19 D20 VREF_6_08 D22 D23 D24 VREF_6_09 D25 VREF_6_10 D28 D29 D30 VREF_6_11 D31 484-PBGAM L23T L23C L24T L24C L25T L25C L26T L26C L27T L27C L28T L28C L29T L29C L30T L30C L31T L31C L32T L32C L33T L33C L34T L34C
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank V9 W9 Y9 U9 AA9 AB9 G16 H13 AB10 AA10 W10 Y10 V10 U13 AB11 AA11 U10 H6 Y11 W11 U11 J7 AB12 AA12 U12 Y12 W12 V11 J8 AB13 AA13 V12 U14 AB14 AA14 J9 Y13 W13 U15 AB15 AA15 AB16 AA16 H14 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) VREF Group 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 5 5 5 5 6 6 I/O IO IO IO IO IO IO VDD15 VSS IO IO IO IO IO VDDIO5 IO IO IO VDD15 IO IO IO VSS IO IO IO IO IO IO VSS IO IO IO VDDIO5 IO IO VSS IO IO VDDIO5 IO IO IO IO VDD15 Pin Description PB17A PB17C PB17D PB18A PB18C PB18D VDD15 VSS PB19A PB19B PB19C PB19D PB20A VDDIO5 PB20C PB20D PB21A VDD15 PB21C PB21D PB22A VSS PB22C PB22D PB23A PB23C PB23D PB24A VSS PB24C PB24D PB25A VDDIO5 PB25C PB25D VSS PB26C PB26D VDDIO5 PB27C PB27D PB28C PB28D VDD15 Additional Function VREF_5_01 PBCK0T PBCK0C VREF_5_02 VREF_5_03 PBCK1T PBCK1C VREF_5_04 VREF_5_05 VREF_5_06 484-PBGAM L35T L35C L36T L36C L37T L37C L38T L38C L39T L39C L40T L40C L41T L41C L42T L42C L43T L43C L44T L44C L45T L45C L46T L46C L47T L47C -
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank Y14 W14 J10 AB17 AA17 U16 Y15 W15 V13 AB18 AA18 J11 V14 V16 Y16 W16 V15 J12 H15 J13 J6 J14 Y17 K8 J15 K7 Y18 K9 W21 W22 F18 V21 V22 U21 U22 E20 G17 G18 J16 J17 T20 J18 T21 F19 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) VREF Group 6 6 7 7 7 7 8 8 8 9 9 9 I/O IO IO VSS IO IO VDDIO5 IO IO VDDIO5 IO IO VSS IO IO IO IO VDD33 VSS VDD15 VSS VDD15 VSS VDD33 VSS VDD15 VDD15 VDD33 VSS VSS VDDGB_B VDD_ANA O O I I VSS VDD_ANA VDD_ANA VDD_ANA VDD_ANA VDDIB VDD_ANA I VSS Pin Description PB29C PB29D VSS PB30C PB30D VDDIO5 PB31C PB31D VDDIO5 PB33C PB33D VSS PB34D PB35B PB36C PB36D VDD33 VSS VDD15 VSS VDD15 VSS VDD33 VSS VDD15 VDD15 VDD33 VSS VSS VDDGB_B VDD_ANA REXT_B REXTN_B REFCLKN_B REFCLKP_B VSS VDD_ANA VDD_ANA VDD_ANA VDD_ANA VDDIB_BC VDD_ANA HDINN_BC VSS Additional Function VREF_5_07 VREF_5_08 484-PBGAM L48T L48C L49T L49C L50T L50C L51T L51C L52T L52C HSN_1 HSP_1 HSN_2 -
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank T22 J19 F20 K16 R20 R21 G19 R22 P21 H16 P22 K17 N22 H17 N21 K18 H18 K19 P20 M22 H19 M21 N20 L16 L17 M20 L22 L18 L21 L20 N16 L19 N17 K22 M16 K21 N18 K20 M17 J20 J21 M18 J22 H20 VREF Group I/O I VDD_ANA VSS VDD_ANA VDDOB O VSS O VDDOB VSS VDDIB VDD_ANA I VSS I VDD_ANA VSS VDD_ANA VDDOB O VSS O VDDOB VSS VSS VDDOB O VSS O VDDOB VDD_ANA VSS VDD_ANA I VSS I VDD_ANA VDDIB VSS VDDOB O VSS O VDDOB Pin Description HDINP_BC VDD_ANA VSS VDD_ANA VDDOB_BC HDOUTN_BC VSS HDOUTP_BC VDDOB_BC VSS VDDIB_BD VDD_ANA HDINN_BD VSS HDINP_BD VDD_ANA VSS VDD_ANA VDDOB_BD HDOUTN_BD VSS HDOUTP_BD VDDOB_BD VSS VSS VDDOB_AD HDOUTP_AD VSS HDOUTN_AD VDDOB_AD VDD_ANA VSS VDD_ANA HDINP_AD VSS HDINN_AD VDD_ANA VDDIB_AD VSS VDDOB_AC HDOUTP_AC VSS HDOUTN_AC VDDOB_AC Additional Function 484-PBGAM HSP_2 HSN_3 HSP_3 HSN_4 HSP_4 HSN_5 HSP_5 HSP_6 HSN_6 HSP_7 HSN_7 HSP_8 HSN_8 -
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank N19 M19 P16 H21 R16 H22 P17 G20 P18 P19 T17 T18 R17 G21 G22 F21 F22 U18 E21 E22 D21 D22 D20 K15 K10 L7 D19 D18 L15 E17 K11 D17 M7 C21 C22 K12 E16 M15 C17 D16 C16 F14 F15 E14 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) VREF Group 7 7 7 7 7 I/O VDD_ANA VSS VDD_ANA I VSS I VDD_ANA VDDIB VDD_ANA VDD_ANA VDD_ANA VDD_ANA VSS I I O O VDD_ANA VDDGB_A VSS O I VDD33 VDD15 VSS VDD15 I I VDD15 I VSS VDD33 VDD15 I I VSS I VDD15 VDD33 IO IO IO IO IO Pin Description VDD_ANA VSS VDD_ANA HDINP_AC VSS HDINN_AC VDD_ANA VDDIB_AC VDD_ANA VDD_ANA VDD_ANA VDD_ANA VSS REFCLKP_A REFCLKN_A REXTN_A REXT_A VDD_ANA VDDGB_A VSS PSYS_RSSIG_ALL PSYS_DOBISTN VDD33 VDD15 VSS VDD15 PBIST_TEST_ENN PLOOP_TEST_ENN VDD15 PASB_PDN VSS VDD33 VDD15 PASB_RESETN PASB_TRISTN VSS PASB_TESTCLK VDD15 VDD33 PT36D PT36B PT35D PT35B PT34D Additional Function VREF_1_07 484-PBGAM HSP_9 HSN_9 HSP_10 HSN_10 -
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank E15 D15 C15 E12 C18 C19 K13 B21 A21 E13 D14 C14 K14 B20 A20 N7 B19 A19 L8 D13 C13 E18 A18 B18 A17 B17 L9 D12 C12 E19 A16 B16 A15 B15 F16 E11 L10 D11 C11 A14 B14 A13 B13 G14 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) VREF Group 8 8 8 8 8 9 9 9 9 9 9 1 1 1 1 1 1 2 2 2 2 3 3 3 3 3 4 4 4 4 4 4 I/O IO IO IO VDDIO1 IO IO VSS IO IO VDDIO1 IO IO VSS IO IO VDD15 IO IO VSS IO IO VDDIO1 IO IO IO IO VSS IO IO VDDIO1 IO IO IO IO VDDIO1 IO VSS IO IO IO IO IO IO VDDIO1 Pin Description PT34B PT33D PT33C VDDIO1 PT32D PT32C VSS PT31D PT31C VDDIO1 PT30D PT30C VSS PT29D PT29C VDD15 PT28D PT28C VSS PT27D PT27C VDDIO1 PT27B PT27A PT26D PT26C VSS PT25D PT25C VDDIO1 PT24D PT24C PT23D PT23C VDDIO1 PT22D VSS PT21D PT21C PT20D PT20C PT19D PT19C VDDIO1 Additional Function VREF_1_08 VREF_1_09 VREF_1_01 VREF_1_02 VREF_1_03 VREF_1_04 484-PBGAM L53C L53T L54C L54T L55C L55T L56C L56T L57C L57T L58C L58T L59C L59T L60C L60T L61C L61T L62C L62T L63C L63T L64C L64T L65C L65T L66C L66T L67C L67T -
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank L11 N15 D10 C10 A12 B12 P6 A11 B11 L12 D9 C9 G15 B10 A10 B9 A9 D8 C8 A22 B8 A8 C7 D7 E9 E6 F6 B7 A7 A6 B6 C6 D6 B1 A5 B5 C5 D5 B2 A4 B4 E10 B22 C4 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) VREF Group 5 5 5 5 5 5 6 6 6 6 1 1 1 1 2 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 I/O VSS VDD15 IO IO IO IO VDD15 IO IO VSS IO IO VDDIO1 IO IO IO IO IO IO VSS IO IO IO IO VDDIO0 IO VDD15 IO IO IO IO IO IO VSS IO IO IO IO VSS IO IO VDDIO0 VSS IO Pin Description VSS VDD15 PT18D PT18C PT17D PT17C VDD15 PT16D PT16C VSS PT15D PT15C VDDIO1 PT14D PT14C PT13D PT13C PT12D PT12C VSS PT12B PT12A PT11D PT11C VDDIO0 PT11A VDD15 PT9D PT9C PT8D PT8C PT7D PT7C VSS PT6D PT6C PT5D PT5C VSS PT4D PT4C VDDIO0 VSS PT2D Additional Function PTCK1C PTCK1T PTCK0C PTCK0T VREF_1_05 VREF_1_06 MPI_RTRY_N MPI_ACK_N M0 M1 MPI_CLK A21/MPI_BURST_N M2 M3 MPI_TEA_N VREF_0_03 D0 TMS A20/MPI_BDIP_N A19/MPI_TSZ1 A18/MPI_TSZ0 D3 D1 D2 TDI TCK PLL_CK1C/PPLL 484-PBGAM L68C L68T L69C L69T L70C L70T L71C L71T L72C L72T L73C L73T L74C L74T L75C L75T L76C L76T L77C L77T L78C L78T L79C L79T L80C L80T L81C L81T L82C L82T L83C
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank D4 A3 B3 F7 C3 E3 P15 R6 R15 T4 W19 Y3 Y19 Y20 T15 T16 U4 T12 T13 T14 T6 T7 T10 T11 G5 H5 J5 V17 W17 W18 M6 N6 U5 U17 V5 V18 R18 R19 T19 U19 U20 V19 V20 W20 0 (TL) 0 (TL) 0 (TL) 0 (TL) 5 (BC) 5 (BC) 5 (BC) 7 (CL) 7 (CL) VREF Group 6 I/O IO O IO VDD15 IO VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO0 VDDIO0 VDDIO0 VDDIO5 VDDIO5 VDDIO5 VDDIO7 VDDIO7 VDD15 VDD15 VDD15 VDD15 VSS VSS VSS VSS VSS VSS VSS VSS Pin Description PT2C PCFG_MPI_IRQ PCCLK VDD15 PDONE VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO0 VDDIO0 VDDIO0 VDDIO5 VDDIO5 VDDIO5 VDDIO7 VDDIO7 VDD15 VDD15 VDD15 VDD15 VSS VSS VSS VSS VSS VSS VSS VSS Additional Function PLL_CK1T/PPLL CFG_IRQ_N/MPI_IRQ_N CCLK DONE 484-PBGAM L83T -
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 44. ORT42G5 484-pin PBGAM (fpBGA) Pinout (Continued)
484-PBGAM VDDIO Bank Y21 Y22 L13 L14 M8 M9 M10 M11 M12 M13 M14 N8 N9 N10 N11 N12 N13 N14 P7 P8 P9 P10 P11 P12 P13 P14 R7 R8 R9 R10 R11 R12 R13 R14 AA1 AA19 AA20 AA21 AA22 AB1 AB19 AB20 AB21 AB22 VREF Group I/O VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Description VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Additional Function 484-PBGAM -
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Lattice Semiconductor
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout
680-PBGAM VDDIO Bank VREF Group AB20 C3 E4 F5 G5 D3 A2 F4 G4 B3 C2 B1 A1 J5 H5 B7 E3 F3 C1 D2 A34 G3 H4 E2 D1 C5 F2 E1 AA13 J4 K5 H3 G2 C9 L5 K4 H2 J3 AA14 M5 F1 G1 K3 J2 -- -- -- -- -- -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- -- -- -- -- -- -- 7 7 -- 7 7 -- 7 7 -- 8 8 8 8 -- 8 8 9 9 -- 9 9 -- 9 9 9 9 -- 9 9 10 10 -- 10 10 10 10 10 I/O Vss VDD33 O I I I VDDIO0 IO IO VDDIO0 IO IO Vss IO IO VDDIO0 IO IO IO IO VSS IO IO IO IO VDDIO0 IO IO VSS IO IO IO IO VDDIO0 IO IO IO IO VSS IO IO IO IO IO
ORCA ORT42G5 and ORT82G5 Data Sheet
Pin Description Vss VDD33 PRD_DATA PRESET_N PRD_CFG_N PPRGRM_N VDDIO0 PL2D PL2C VDDIO0 PL3D PL3C VSS PL4D PL4C VDDIO0 PL4B PL4A PL5D PL5C VSS PL5B PL5A PL6D PL6C VDDIO0 PL7D PL7C VSS PL7B PL7A PL8D PL8C VDDIO0 PL8B PL8A PL9D PL9C VSS PL9B PL10D PL10C PL11D PL11C
Additional Function -- -- RD_DATA/TDO RESET_N RD_CFG_N PRGRM_N -- PLL_CK0C/HPPLL PLL_CK0T/HPPLL -- -- VREF_0_07 -- D5 D6 -- -- VREF_0_08 HDC LDC_N -- -- -- TESTCFG D7 -- VREF_0_09 A17/PPC_A31 -- -- -- CS0_N CS1 -- -- -- -- -- -- -- INIT_N DOUT VREF_0_10 A16/PPC_A30
680-PBGAM -- -- -- -- -- -- -- L21C_A0 L21T_A0 -- L22C_D0 L22T_D0 -- L23C_A0 L23T_A0 -- L24C_A0 L24T_A0 L25C_D0 L25T_D0 -- L26C_D0 L26T_D0 L27C_D0 L27T_D0 -- L28C_D0 L28T_D0 -- L29C_D0 L29T_D0 L30C_D0 L30T_D0 -- L31C_D0 L31T_D0 L32C_D0 L32T_D0 -- -- L33C_A0 L33T_A0 L34C_D0 L34T_D0
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ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group AA15 L4 N5 M4 AA3 L3 K2 H1 J1 V18 N4 P5 M3 L2 AC2 K1 L1 P4 P3 V19 M2 M1 N2 N1 N3 R4 P2 R3 W16 R5 P1 R1 T5 T4 T3 T2 W17 U1 T1 U4 U5 R2 U2 V1 -- 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 10 1 1 -- 1 1 1 1 -- 2 2 2 2 -- 2 2 2 2 -- 2 2 3 3 -- 3 3 3 -- 3 3 3 3 3 4 4 -- 4 4 4 4 -- 4 4 I/O VSS IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDDIO7 IO IO IO VSS IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO7 IO IO Pin Description VSS PL11B PL12D PL12C VDDIO7 PL12B PL12A PL13D PL13C VSS PL13B PL13A PL14D PL14C VDDIO7 PL14B PL14A PL15D PL15C VSS PL15B PL15A PL16D PL16C VDDIO7 PL16B PL17D PL17C VSS PL17B PL18D PL18C PL18B PL18A PL19D PL19C VSS PL19B PL19A PL20D PL20C VDDIO7 PL20B PL20A Additional Function -- -- A15/PPC_A29 A14/PPC_A28 -- -- -- VREF_7_01 D4 -- -- -- RDY/BUSY_N/RCLK VREF_7_02 -- -- -- A13/PPC_A27 A12/PPC_A26 -- -- -- -- -- -- -- A11/PPC_A25 VREF_7_03 -- -- -- -- -- -- RD_N/MPI_STRB_N VREF_7_04 -- -- -- PLCK0C PLCK0T -- -- -- 680-PBGAM -- -- L1C_D0 L1T_D0 -- L2C_D0 L2T_D0 L3C_A0 L3T_A0 -- L4C_D0 L4T_D0 L5C_D0 L5T_D0 -- L6C_A0 L6T_A0 L7C_A0 L7T_A0 -- L8C_A0 L8T_A0 L9C_A0 L9T_A0 -- -- L10C_D0 L10T_D0 -- -- L11C_A0 L11T_A0 L12C_A0 L12T_A0 L13C_A0 L13T_A0 -- L14C_A0 L14T_A0 L15C_A0 L15T_A0 -- L16C_D0 L16T_D0
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ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group W18 V2 V3 W19 V4 V5 W4 W3 W1 Y1 Y2 AA1 Y13 Y4 Y3 Y5 W5 U3 AB1 AA2 AB2 AC1 Y14 AA4 AB4 AB3 W2 AD1 AE1 AD2 AC3 AC4 AF1 AE2 AB5 AA5 Y15 AD3 AG1 AF2 AD4 AE3 AD5 AC5 -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 5 5 -- 5 5 5 5 5 5 5 5 -- 5 5 6 6 -- 6 6 6 6 -- 6 6 6 -- 7 7 7 7 7 8 8 8 8 -- 8 8 8 8 8 8 8 I/O VSS IO IO VSS IO IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO VDDIO7 IO IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO Pin Description VSS PL21D PL21C VSS PL21B PL21A PL22D PL22C PL22B PL22A PL23D PL23C VSS PL23B PL23A PL24D PL24C VDDIO7 PL24B PL24A PL25D PL25C VSS PL25B PL26D PL26C VDDIO7 PL26B PL27D PL27C PL27B PL27A PL28D PL28C PL29D PL29C VSS PL29B PL30D PL30C PL30B PL30A PL31D PL31C Additional Function -- A10/PPC_A24 A9/PPC_A23 -- -- -- A8/PPC_A22 VREF_7_05 -- -- -- -- -- -- -- PLCK1C PLCK1T -- -- -- VREF_7_06 A7/PPC_A21 -- -- A6/PPC_A20 A5/PPC_A19 -- -- WR_N/MPI_RW VREF_7_07 -- -- A4/PPC_A18 VREF_7_08 A3/PPC_A17 A2/PPC_A16 -- -- A1/PPC_A15 A0/PPC_A14 -- -- DP0 DP1 680-PBGAM -- L17C_A0 L17T_A0 -- L18C_A0 L18T_A0 L19C_A0 L19T_A0 L20C_A0 L20T_A0 L21C_D0 L21T_D0 -- L22C_A0 L22T_A0 L23C_A0 L23T_A0 -- L24C_D0 L24T_D0 L25C_D0 L25T_D0 -- -- L26C_A0 L26T_A0 -- -- L27C_D0 L27T_D0 L28C_A0 L28T_A0 L29C_D0 L29T_D0 L30C_A0 L30T_A0 -- -- L31C_D0 L31T_D0 L32C_D0 L32T_D0 L33C_A0 L33T_A0
101
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group Y20 AG2 AH1 AF3 AG3 AL7 AE4 AF4 AE5 AF5 R21 AJ1 AH2 AM5 AK1 AJ2 R22 AG4 AH3 AL1 AK2 AM9 AM1 AL2 AJ3 T16 AJ4 AH4 AK3 AN2 AG5 AH5 AN1 AM2 T17 AL3 AK4 T18 AM3 AN3 AJ5 AL4 T19 AK5 -- 7 (CL) 7 (CL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) -- -- 6 (BL) -- -- -- -- -- 8 8 1 1 -- 1 1 1 1 -- 2 2 -- 2 2 -- 3 3 3 3 -- 3 3 4 -- 4 4 4 -- 4 4 4 4 -- 4 4 -- -- -- -- -- -- -- I/O VSS IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO VDDIO6 IO IO VSS IO IO IO IO VDDIO6 IO IO IO VSS IO IO IO VDDIO6 IO IO IO IO VSS IO IO VSS I VDDIO6 IO VDD33 VSS VDD33 Pin Description VSS PL31B PL31A PL32D PL32C VDDIO6 PL32B PL32A PL33D PL33C VSS PL34D PL34C VDDIO6 PL34B PL34A VSS PL35B PL35A PL36D PL36C VDDIO6 PL36B PL36A PL37D VSS PL37B PL37A PL38C VDDIO6 PL38B PL38A PL39D PL39C VSS PL39B PL39A VSS PTEMP VDDIO6 LVDS_R VDD33 VSS VDD33 Additional Function -- -- -- D8 VREF_6_01 -- -- -- D9 D10 -- -- VREF_6_02 -- -- -- -- D11 D12 -- -- -- VREF_6_03 D13 -- -- -- VREF_6_04 -- -- -- -- PLL_CK7C/HPPLL PLL_CK7T/HPPLL -- -- -- -- PTEMP -- LVDS_R -- -- -- 680-PBGAM -- L34C_D0 L34T_D0 L1C_A0 L1T_A0 -- L2C_A0 L2T_A0 L3C_A0 L3T_A0 -- L4C_D0 L4T_D0 -- L5C_D0 L5T_D0 -- L6C_D0 L6T_D0 L7C_D0 L7T_D0 -- L8C_D0 L8T_D0 -- -- L9C_A0 L9T_A0 -- -- L10C_A0 L10T_A0 L11C_D0 L11T_D0 -- L12C_D0 L12T_D0 -- -- -- -- -- -- --
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ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group AM4 AL5 AN7 AP3 AP4 AN4 U16 AK6 AK7 AL6 AM6 AP1 AN5 AP5 AK8 U17 AP6 AP7 AM7 AN6 AP2 AL8 AL9 AK9 U18 AN8 AM8 AN9 AP8 AK10 AL10 AP9 U19 AM10 AM11 AK11 AN10 AP10 AN11 AP11 V16 AL12 AK12 AN12 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 5 5 -- 5 5 5 -- 5 5 5 5 -- 6 6 6 -- 6 6 6 6 -- 7 7 7 -- 7 7 7 7 7 7 8 -- 8 8 8 8 8 9 9 -- 9 9 9 I/O IO IO VDDIO6 IO IO IO VSS IO IO IO IO VDDIO6 IO IO IO VSS IO IO IO IO VDDIO6 IO IO IO VSS IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO VSS IO IO IO Pin Description PB2A PB2B VDDIO6 PB2C PB2D PB3B VSS PB3C PB3D PB4A PB4B VDDIO6 PB4C PB4D PB5B VSS PB5C PB5D PB6A PB6B VDDIO6 PB6C PB6D PB7B VSS PB7C PB7D PB8A PB8B PB8C PB8D PB9B VSS PB9C PB9D PB10B PB10C PB10D PB11A PB11B VSS PB11C PB11D PB12A Additional Function DP2 -- -- PLL_CK6T/PPLL PLL_CK6C/PPLL -- -- -- -- VREF_6_05 DP3 -- -- -- -- -- VREF_6_06 D14 -- -- -- D15 D16 -- -- D17 D18 -- -- VREF_6_07 D19 -- -- D20 D21 -- VREF_6_08 D22 -- -- -- D23 D24 -- 680-PBGAM L13T_D0 L13C_D0 -- L14T_A0 L14C_A0 -- -- L15T_A0 L15C_A0 L16T_A0 L16C_A0 -- L17T_A0 L17C_A0 -- -- L18T_D0 L18C_D0 L19T_D0 L19C_D0 -- L20T_A0 L20C_A0 -- -- L21T_A0 L21C_A0 L22T_D0 L22C_D0 L23T_A0 L23C_A0 -- -- L24T_A0 L24C_A0 -- L25T_A0 L25C_A0 L26T_A0 L26C_A0 -- L27T_A0 L27C_A0 L28T_A0
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group AM12 AP12 AP13 AM13 AN14 V17 AP14 AP15 AK13 AK14 AM14 AL14 AP17 AP16 AM15 AN16 AM17 AM16 AP18 AP19 AL16 AK15 N22 AN18 AN19 AP20 AP21 AL17 AK16 P13 AM19 AM18 P14 AN20 AM20 AK17 AL18 AL11 AP22 AN21 AM22 AM21 AP23 AN22 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 9 9 9 9 9 -- 10 10 10 10 10 10 11 11 11 11 11 11 11 11 1 1 -- 1 1 1 1 1 1 -- 2 2 -- 2 2 2 2 -- 2 2 2 2 3 3 I/O IO IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO VSS IO IO VSS IO IO IO IO VDDIO5 IO IO IO IO IO IO Pin Description PB12B PB12C PB12D PB13A PB13B VSS PB13C PB13D PB14A PB14B PB14C PB14D PB15A PB15B PB15C PB15D PB16A PB16B PB16C PB16D PB17A PB17B VSS PB17C PB17D PB18A PB18B PB18C PB18D VSS PB19A PB19B VSS PB19C PB19D PB20A PB20B VDDIO5 PB20C PB20D PB21A PB21B PB21C PB21D Additional Function -- VREF_6_09 D25 -- -- -- D26 D27 -- -- VREF_6_10 D28 -- -- D29 D30 -- -- VREF_6_11 D31 -- -- -- -- -- -- -- VREF_5_01 -- -- -- -- -- PBCK0T PBCK0C -- -- -- VREF_5_02 -- -- -- -- VREF_5_03 680-PBGAM L28C_A0 L29T_A0 L29C_A0 L30T_D0 L30C_D0 -- L31T_A0 L31C_A0 L32T_A0 L32C_A0 L33T_A0 L33C_A0 L34T_A0 L34C_A0 L35T_D0 L35C_D0 L36T_A0 L36C_A0 L37T_A0 L37C_A0 L1T_D0 L1C_D0 -- L2T_A0 L2C_A0 L3T_A0 L3C_A0 L4T_D0 L4C_D0 -- L5T_A0 L5C_A0 -- L6T_A0 L6C_A0 L7T_D0 L7C_D0 -- L8T_D0 L8C_D0 L9T_A0 L9C_A0 L10T_D0 L10C_D0
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group AL19 AK18 P15 AP24 AN23 AP25 AP26 AL13 AL20 AK19 AK20 AL21 P20 AN24 AM23 AN26 AN25 AL15 AK21 AL22 AM24 AL23 P21 AP27 AN27 AL24 AM25 AN13 AP28 AP29 AN29 P22 AM27 AN28 AM26 AK22 AK23 AL25 R13 AP30 AP31 AK24 AN15 AM29 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 3 3 -- 3 3 3 3 -- 3 3 3 3 -- 4 4 4 4 -- 4 4 4 4 -- 5 5 5 5 -- 5 5 6 -- 6 6 6 6 6 7 -- 7 7 7 -- 7 I/O IO IO VSS IO IO IO IO VDDIO5 IO IO IO IO VSS IO IO IO IO VDDIO5 IO IO IO IO VSS IO IO IO IO VDDIO5 IO IO IO VSS IO IO IO IO IO IO VSS IO IO IO VDDIO5 IO Pin Description PB22A PB22B VSS PB22C PB22D PB23A PB23B VDDIO5 PB23C PB23D PB24A PB24B VSS PB24C PB24D PB25A PB25B VDDIO5 PB25C PB25D PB26A PB26B VSS PB26C PB26D PB27A PB27B VDDIO5 PB27C PB27D PB28B VSS PB28C PB28D PB29B PB29C PB29D PB30B VSS PB30C PB30D PB31B VDDIO5 PB31C Additional Function -- -- -- -- -- -- -- -- PBCK1T PBCK1C -- -- -- -- -- -- -- -- -- VREF_5_04 -- -- -- -- VREF_5_05 -- -- -- -- -- -- -- -- VREF_5_06 -- -- -- -- -- -- -- -- -- VREF_5_07 680-PBGAM L11T_D0 L11C_D0 -- L12T_D0 L12C_D0 L13T_A0 L13C_A0 -- L14T_D0 L14C_D0 L15T_D0 L15C_D0 -- L16T_D0 L16C_D0 L17T_A0 L17C_A0 -- L18T_D0 L18C_D0 L19T_D0 L19C_D0 -- L20T_A0 L20C_A0 L21T_D0 L21C_D0 -- L22T_A0 L22C_A0 -- -- L23T_D0 L23C_D0 -- L24T_A0 L24C_A0 -- -- L25T_A0 L25C_A0 -- -- L26T_A0
105
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group AM28 AN30 R14 AK25 AL26 AN17 AL27 AL28 AN31 R15 AK26 AM30 AL29 AK27 R20 AL30 AK29 AK28 AA16 AP32 AP33 AN32 AM31 AA17 AM32 AL31 AM33 AA18 AK30 AL32 AA19 AB16 AK31 AJ30 AK33 AK34 AJ31 AJ33 AJ34 AH30 AH31 AH32 AH33 AH34 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 7 7 -- 7 7 -- 8 8 8 -- 8 9 9 9 -- 9 9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O IO IO VSS IO IO VDDIO5 IO IO IO VSS IO IO IO IO VSS IO IO VDD33 VDD15 IO IO IO IO VDD15 VDD33 IO IO VDD15 IO IO VDD15 VDD15 VDD33 IO IO IO IO IO IO IO IO O VSS VDDGB_B Pin Description PB31D PB32B VSS PB32C PB32D VDDIO5 PB33C PB33D PB34B VSS PB34D PB35B PB35D PB36B VSS PB36C PB36D VDD33 VDD15 PSCHAR_LDIO9 PSCHAR_LDIO8 PSCHAR_LDIO7 PSCHAR_LDIO6 VDD15 VDD33 PSCHAR_LDIO5 PSCHAR_LDIO4 VDD15 PSCHAR_LDIO3 PSCHAR_LDIO2 VDD15 VDD15 VDD33 PSCHAR_LDIO1 PSCHAR_LDIO0 PSCHAR_CKIO1 PSCHAR_CKIO0 PSCHAR_XCK PSCHAR_WDSYNC PSCHAR_CV PSCHAR_BYTSYNC ATMOUT_B (no connect) VSS VDDGB_B Additional Function -- -- -- -- -- -- -- VREF_5_08 -- -- -- -- VREF_5_09 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 680-PBGAM L26C_A0 -- -- L27T_D0 L27C_D0 -- L28T_A0 L28C_A0 -- -- -- -- -- -- -- L29T_D0 L29C_D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group AA32 AF30 AF31 AE30 AE31 AB32 AD30 AD32 AF33 AC32 AF34 AE32 AD31 K32 AE33 AF32 AE34 AC30 AG30 AB30 AD33 AG31 AD34 AC31 AC33 AG32 AC34 AB31 AG33 AA30 AB33 AG34 AB34 AA31 Y30 AA33 H30 AA34 Y31 H31 W30 Y33 H32 Y34 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VDD_ANA -- -- I I VSS VDDIB VDD_ANA I VSS I VDD_ANA VSS VDD_ANA O VSS O VDDOB VSS VDDIB I VSS I VSS O VSS O VDDOB VSS VDDIB I VSS I VSS VDDOB O VSS O VDDOB VSS VDDIB I VSS I Pin Description VDD_ANA REXT_B REXTN_B REFCLKN_B REFCLKP_B VSS VDDIB_BA VDD_ANA HDINN_BA VSS HDINP_BA VDD_ANA VSS VDD_ANA HDOUTN_BA VSS HDOUTP_BA VDDOB_BA VSS VDDIB_BB HDINN_BB VSS HDINP_BB VSS HDOUTN_BB VSS HDOUTP_BB VDDOB_BB VSS VDDIB_BC HDINN_BC VSS HDINP_BC VSS VDDOB_BC HDOUTN_BC VSS HDOUTP_BC VDDOB_BC VSS VDDIB_BD HDINN_BD VSS HDINP_BD Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 680-PBGAM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group W31 V30 W33 H33 W34 V31 H34 J32 U31 T34 M32 T33 U30 T31 R34 N32 R33 T30 U32 R31 P34 U33 P33 R30 P31 N34 U34 N33 P30 V32 M34 V33 M33 N31 M31 L34 V34 L33 N30 K34 K33 M30 L32 L31 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VSS VDDOB O VSS O VDDOB VSS VSS VDDOB O VSS O VDDOB VSS I VSS I VDDIB VSS VDDOB O VSS O VDDOB VSS I VSS I VDDIB VSS O VSS O VDDOB VSS I VSS I VDDIB O O VDDOB VDD_ANA VSS Pin Description VSS VDDOB_BD HDOUTN_BD VSS HDOUTP_BD VDDOB_BD VSS VSS VDDOB_AD HDOUTP_AD VSS HDOUTN_AD VDDOB_AD VSS HDINP_AD VSS HDINN_AD VDDIB_AD VSS VDDOB_AC HDOUTP_AC VSS HDOUTN_AC VDDOB_AC VSS HDINP_AC VSS HDINN_AC VDDIB_AC VSS HDOUTP_AB VSS HDOUTN_AB VDDOB_AB VSS HDINP_AB VSS HDINN_AB VDDIB_AB HDOUTP_AA HDOUTN_AA VDDOB_AA VDD_ANA VSS Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 680-PBGAM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group P32 J34 J33 R32 L30 K31 K30 J31 J30 Y32 G34 G33 G32 G31 F33 G30 F31 F30 E31 AB17 AB18 D32 E30 AB19 D31 C32 C31 AJ32 B32 A33 B31 A32 AK32 AB21 A31 B30 AB22 C30 D30 B13 E29 E28 AN33 D29 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 7 -- 7 7 -- 7 7 -- 8 I/O VDD_ANA I I VDD_ANA VDDIB -- -- O O VDD_ANA VDDGB_A VSS O I I I O I VDD33 VDD15 VDD15 I I VDD15 I I VDD33 VDD15 I I I I VDD15 VSS VDD33 IO VSS IO IO VDDIO1 IO IO VSS IO Pin Description VDD_ANA HDINP_AA HDINN_AA VDD_ANA VDDIB_AA REFCLKP_A REFCLKN_A REXTN_A REXT_A VDD_ANA VDDGB_A VSS ATMOUT_A (no connect) PRESERVE01 (no connect) PRESERVE02 (no connect) PRESERVE03 (no connect) PSYS_RSSIG_ALL PSYS_DOBISTN VDD33 VDD15 VDD15 PBIST_TEST_ENN PLOOP_TEST_ENN VDD15 PASB_PDN PMP_TESTCLK VDD33 VDD15 PASB_RESETN PASB_TRISTN PMP_TESTCLK_ENN PASB_TESTCLK VDD15 VSS VDD33 PT36D VSS PT36B PT35D VDDIO1 PT35B PT34D Vss PT34B Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_07 -- -- 680-PBGAM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group B29 C29 B15 E27 E26 AP34 A30 A29 E25 B17 E24 B28 C28 B2 D28 C27 D27 E23 E22 D26 D25 B33 D24 D23 C26 C25 D11 E21 E20 D22 D21 E34 A28 B26 B25 D13 B27 A27 A26 N13 C24 C22 C23 D15 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 8 8 -- 8 8 -- 8 9 9 -- 9 9 9 -- 9 9 9 9 9 1 1 -- 1 1 1 1 -- 1 1 2 2 -- 2 2 2 -- 2 3 3 -- 3 3 3 -- I/O IO IO VDDIO1 IO IO Vss IO IO IO VDDIO1 IO IO IO Vss IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO1 IO IO IO IO Vss IO IO IO VDDIO1 IO IO IO Vss IO IO IO VDDIO1 Pin Description PT33D PT33C VDDIO1 PT32D PT32C Vss PT32B PT31D PT31C VDDIO1 PT31A PT30D PT30C Vss PT30A PT29D PT29C PT29B PT29A PT28D PT28C Vss PT28B PT28A PT27D PT27C VDDIO1 PT27B PT27A PT26D PT26C Vss PT26B PT25D PT25C VDDIO1 PT25B PT24D PT24C Vss PT24B PT23D PT23C VDDIO1 Additional Function -- VREF_1_08 -- -- -- -- -- -- VREF_1_09 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_01 -- -- -- -- -- VREF_1_02 -- -- -- -- -- -- -- VREF_1_03 -- -- -- -- -- 680-PBGAM L1C_A0 L1T_A0 -- L2C_A0 L2T_A0 -- -- L3C_D3 L3T_D3 -- -- L4C_A0 L4T_A0 -- -- L5C_A0 L5T_A0 L6C_A0 L6T_A0 L7C_A0 L7T_A0 -- L8C_A0 L8T_A0 L9C_A0 L9T_A0 -- L10C_A0 L10T_A0 L11C_A0 L11T_A0 -- -- L12C_A0 L12T_A0 -- -- L13C_A0 L13T_A0 -- -- L14C_A0 L14T_A0 --
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group B24 D20 D19 N14 E19 E18 C21 C20 A25 A24 B23 A23 N15 E17 E16 B22 B21 C18 C19 N20 A22 A21 N21 D17 D18 B20 B19 A20 A19 A18 B18 Y21 C17 D16 A17 B16 E15 E14 A16 A15 Y22 D14 C16 C15 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 0 (TL) 0 (TL) 3 3 3 -- 3 3 4 4 4 4 4 4 -- 4 4 4 4 4 4 -- 5 5 -- 5 5 5 5 5 5 5 5 -- 5 5 6 6 6 6 6 6 -- 6 1 1 I/O IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO IO IO Vss IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO Pin Description PT23B PT22D PT22C Vss PT22B PT22A PT21D PT21C PT21B PT21A PT20D PT20C Vss PT20B PT20A PT19D PT19C PT19B PT19A Vss PT18D PT18C Vss PT18B PT18A PT17D PT17C PT17B PT17A PT16D PT16C Vss PT16B PT16A PT15D PT15C PT15B PT15A PT14D PT14C Vss PT14B PT13D PT13C Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_04 -- -- -- PTCK1C PTCK1T -- -- -- PTCK0C PTCK0T -- -- VREF_1_05 -- -- -- -- -- -- -- -- -- VREF_1_06 -- -- MPI_RTRY_N MPI_ACK_N 680-PBGAM -- L15C_A0 L15T_A0 -- L16C_A0 L16T_A0 L17C_A0 L17T_A0 L18C_A0 L18T_A0 L19C_A0 L19T_A0 -- L20C_A0 L20T_A0 L21C_A0 L21T_A0 L22C_A0 L22T_A0 -- L23C_A0 L23T_A0 -- L24C_A0 L24T_A0 L25C_A0 L25T_A0 L26C_A0 L26T_A0 L27C_A0 L27T_A0 -- L28C_D0 L28T_D0 L29C_D0 L29T_D0 L30C_A0 L30T_A0 L31C_A0 L31T_A0 -- -- L1C_A0 L1T_A0
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ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group D7 C14 B14 A14 A13 AA20 E12 E13 C13 C12 B12 A12 D12 C11 B11 A11 A10 AA21 B10 E11 D10 C10 A9 B9 AA22 E10 A8 B8 D9 C8 E9 D8 AB13 A7 A6 C7 B6 E8 E7 A5 B5 AB14 C6 D6 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) -- 1 1 1 1 -- 2 2 2 2 2 2 3 3 3 3 3 -- 3 3 3 3 4 4 -- 4 4 4 4 4 5 5 -- 5 5 5 5 5 5 6 6 -- 6 6 I/O VDDIO0 IO IO IO IO Vss IO IO IO IO IO IO IO IO IO IO IO Vss IO IO IO IO IO IO Vss IO IO IO IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO Pin Description VDDIO0 PT13B PT13A PT12D PT12C Vss PT12B PT12A PT11D PT11C PT11B PT11A PT10D PT10C PT10B PT9D PT9C Vss PT9B PT8D PT8C PT8B PT7D PT7C Vss PT7B PT6D PT6C PT6B PT6A PT5D PT5C Vss PT5B PT5A PT4D PT4C PT4B PT4A PT3D PT3C Vss PT3B PT3A Additional Function -- -- VREF_0_01 M0 M1 -- MPI_CLK A21/MPI_BURST_N M2 M3 VREF_0_02 MPI_TEA_N -- -- -- VREF_0_03 -- -- -- D0 TMS -- A20/MPI_BDIP_N A19/MPI_TSZ1 -- -- A18/MPI_TSZ0 D3 VREF_0_04 -- D1 D2 -- -- VREF_0_05 TDI TCK -- -- -- VREF_0_06 -- -- -- 680-PBGAM -- L2C_A0 L2T_A0 L3C_A0 L3T_A0 -- L4C_A0 L4T_A0 L5C_A0 L5T_A0 L6C_A0 L6T_A0 L7C_D0 L7T_D0 -- L8C_A0 L8T_A0 -- -- L9C_D0 L9T_D0 -- L10C_A0 L10T_A0 -- -- L11C_A0 L11T_A0 L12C_D0 L12T_D0 L13C_D0 L13T_D0 -- L14C_A0 L14T_A0 L15C_D0 L15T_D0 L16C_A0 L16T_A0 L17C_A0 L17T_A0 -- L18C_A0 L18T_A0
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ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group C4 B4 A4 A3 D5 E6 D4 E5 AB15 AL33 AL34 AM34 AN34 B34 C33 C34 D33 D34 E32 E33 F32 F34 N16 N17 N18 N19 P16 P17 P18 P19 R16 R17 R18 R19 T13 T14 T15 T20 T21 T22 U13 U14 U15 U20 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6 6 6 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O IO IO IO IO O IO IO VDD33 Vss VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Pin Description PT2D PT2C PT2B PT2A PCFG_MPI_IRQ PCCLK PDONE VDD33 Vss VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Additional Function PLL_CK1C/PPLL PLL_CK1T/PPLL -- -- CFG_IRQ_N/MPI_IRQ_N CCLK DONE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 680-PBGAM L19C_A0 L19T_A0 L20C_A0 L20T_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group U21 U22 V13 V14 V15 V20 V21 V22 W13 W14 W15 W20 W21 W22 Y16 Y17 Y18 Y19 T32 W32 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 NC NC Pin Description VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 NC NC Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 680-PBGAM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Package Thermal Characteristics Summary
There are three thermal parameters that are in common use: JA, JC, and JC. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow.
JA
This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.): JA = TJ - TA Q (1)
where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power. Experimentally, JA is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip's heater resistor, the chip's temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that JA is expressed in units of C/W.
JC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance and it is defined by: JC = TJ - TC Q 114 (2)
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the JA measurements described above, besides the other parameters measured, an additional temperature reading, TC, is made with a thermocouple attached at top-dead-center of the case. JC is also expressed in units of C/W.
JC
This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is defined by: JC = TJ - TC Q (3)
The parameters in this equation have been defined above. However, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates JC from JC. JC is a true thermal resistance and is expressed in units of C/W.
JB
This is the thermal resistance from junction to board. It is defined by: JB = TJ - TB Q (4)
where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters on the right-hand side have been defined above. This is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. Note that JB is expressed in units of C/W and that this parameter and the way it is measured are still being discussed by the JEDEC committee.
FPSC Maximum Junction Temperature
Once the power dissipated by the FPSC has been determined, the maximum junction temperature of the FPSC can be found. This is needed to determine if speed derating of the device from the 85 C junction temperature used in all of the delay tables is needed. Using the maximum ambient temperature, TAmax, and the power dissipated by the device, Q (expressed in C), the maximum junction temperature is approximated by: TJmax = TAmax + (Q JB) (5)
Package Thermal Characteristics
The thermal characteristics of the 484-ball PBGAM (fpBGA with heat spreader) used for the ORT42G5, the 680ball PBGAM (fpBGA with heat spreader) and the 680-ball fpBGA used for the ORT82G5 are available in the Thermal Management section of the Lattice web site at www.latticesemi.com.
Heat Sink Vendors for BGA Packages
The estimated worst-case power requirements for the ORT42G5 and ORT82G5 are in the 3 W to 5 W range. Consequently, for most applications an external heat sink will be required. Table 46 lists, in alphabetical order, heat sink vendors who advertise heat sinks aimed at the BGA market.
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Lattice Semiconductor
Table 46. Heat Sink Vendors
Vendor Aavid Thermalloy Chip Coolers IERC R-Theta Sanyo Denki Wakefield Thermal Solutions
ORCA ORT42G5 and ORT82G5 Data Sheet
Location Concord, NH Warwick, RI Burbank, CA Buffalo, NY Torrance, CA Pelham, NH
Phone (603) 224-9988 (800) 227-0254 (818) 842-7277 (800) 388-5428 (310) 783-5400 (800) 325-1426
Package Parasitics
The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Table 47 lists eight parasitics associated with the ORCA packages. These parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. Resistance values are in m. The parasitic values in Table 47 are for the circuit model of bond wire and package lead parasitics. If the mutual capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added to each of the C1 and C2 capacitors. Table 47. ORCA Typical Package Parasitics
LSW 3.8 LMW 1.3 RW 250 C1 1.0 C2 1.0 CM 0.3 LSL 2.8-5 LML 0.5 -1
Figure 41. Package Parasitics
LSW PAD N RW LSL
Pad N
C1 C2 LML Circuit Board Pads
Package Pads
LMW CM
PAD N + 1 LSW RW C1 LSL C2
Pad N+1
Package Outline Drawings
Package Outline Drawings for the 484-ball PBGAM (fpBGA) used for the ORT42G5 and 680-ball PBGAM (fpBGA) used for the ORT82G5 are available in the Package Diagrams section of the Lattice Semiconductor web site at www.latticesemi.com.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Part Number Description
ORTX2G5 - X XXX XXX X XX Device Family ORT42G5 = 4 SERDES Channels ORT82G5 = 8 SERDES Channels Speed Grade Package BM = Fine-Pitch Plastic Ball Grid Array BMN = Lead-Free Fine-Pitch Plastic Ball Grid Array F = Fine-Pitch Plastic Ball Grid Array FN = Lead-Free Fine-Pitch Plastic Ball Grid Array Optional Suffix Blank = Production ES = Engineering Samples Grade C = Commercial I = Industrial Ball Count 484 680
Device Type Options
Device ORT42G5 ORT82G5 Voltage 1.5V internal 3.3/2.5/1.8/ 1.5V I/O 1.5V internal 3.3/2.5/1.8/ 1.5V I/O
Ordering Information
Conventional Packaging
Commercial1
Device Family ORT42G5 Part Number ORT42G5-3BM484C ORT42G5-2BM484C ORT42G5-1BM484C ORT82G5-3F680C ORT82G5-2F680C ORT82G5 ORT82G5-1F680C ORT82G5-3BM680C2 ORT82G5-2BM680C2 ORT82G5-1BM680C
2 2
Speed Grade 3 2 1 3 2 1 3 2 1 PBGAM PBGAM PBGAM
Package Type
Ball Count 484 484 484 680 680 680 680 680 680
Grade C C C C C C C C C
PBGAM (No Heat Spreader) PBGAM (No Heat Spreader) PBGAM (No Heat Spreader) PBGAM (With Heat Spreader) PBGAM (With Heat Spreader) PBGAM (With Heat Spreader)
1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only. 2. BM680 package was converted to F680 via PCN#09A-08.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Industrial1
Device Family ORT42G5
Part Number ORT42G5-2BM484I ORT42G5-1BM484I ORT82G5-2F680I ORT82G5-1F680I ORT82G5-2BM680I
2
Speed Grade 2 1 2 1 2 1 PBGAM PBGAM
Package Type
Ball Count 484 484 680 680 680 680
Grade I I I I I I
PBGAM (No Heat Spreader) PBGAM (No Heat Spreader) PBGAM (With Heat Spreader) PBGAM (With Heat Spreader)
ORT82G5
ORT82G5-1BM680I2
1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only. 2. BM680 package was converted to F680 via PCN#09A-08.
Lead-Free Packaging
Commercial1
Device Family ORT42G5 Part Number ORT42G5-3BMN484C ORT42G5-2BMN484C ORT42G5-1BMN484C ORT82G5-3FN680C ORT82G5 ORT82G5-2FN680C ORT82G5-1FN680C Speed Grade 3 2 1 3 2 1 Package Type Lead-Free PBGAM Lead-Free PBGAM Lead-Free PBGAM Lead-Free FPGA (No Heat Spreader) Lead-Free FPGA (No Heat Spreader)
2
Ball Count 484 484 484 680 680 680
Grade C C C C C C
Lead-Free FPGA (No Heat Spreader)2
2
1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster. 2. Refer to the Thermal Management document at www.latticesemi.com for JA and JC information.
Industrial1
Device Family ORT42G5 ORT82G5 Part Number ORT42G5-2BMN484I ORT42G5-1BMN484I ORT82G5-2FN680I ORT82G5-1FN680I Speed Grade 2 1 2 1 Package Type Lead-Free PBGAM Lead-Free PBGAM Lead-Free FPGA (No Heat Spreader)
2
Ball Count 484 484 680 680
Grade I I I I
Lead-Free FPGA (No Heat Spreader)2
1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster. 2. Refer to the Thermal Management document at www.latticesemi.com for JA and JC information.
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Technical Support Assistance
Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com
Revision History
Date -- July 2008 Version -- 07.0 Previous Lattice releases. BM680 conversion to F680 per PCN#09A-08. Change Summary
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